Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
1998-09-30
2001-09-18
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185210, C365S230030
Reexamination Certificate
active
06292392
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a rewritable non-volatile memory device such as an EEPROM (electrically erasable and programmable read only memory) or a flash memory.
2. Description of the Related Art
First, the general structure of a non-volatile memory device will be described.
FIG. 7
illustrates the structure of a memory cell in a non-volatile memory device. The memory cell MC includes a control gate CG, a floating gate FG, a source S, and a drain D. The memory cell MC stores data in accordance with electrons injected to the floating gate FG.
FIG. 8
illustrates the block structure of a NOR type flash memory, and particularly shows the relationship between an X-decoder XD and word lines WL
1
, WL
2
, . . . , WLm.
Flash memories define one class of non-volatile memory devices. A typical connection method for memory cells of a flash memory is referred to as a NOR type. In a NOR type flash memory FM shown in
FIG. 8
, mxn memory cells MC are coupled in a matrix, designated block BLK
1
or BLK
2
.
The structure of each of the blocks BLK
1
and BLK
2
will now be described. To each of m word lines WL
1
, . . . , WLm, n control gates CG are coupled. To each of n bit lines BL
1
, . . . , BLn, m drains D are coupled. Sources S of all memory cells MC are coupled to a common. Hereinafter, being coupled to a common shall meant that each device is coupled together via one or more lines. The details of an erase operation of such a NOR type flash memory will be described in detail later. Since the sources S are coupled to a common within each block BLK
1
or BLK
2
, erasing any data stored in a given memory cell MC results in erasing all the data stored in the entire block. In other words, it is impossible to selectively erase the data in any single memory cell in a bit-by-bit manner. The word lines in one block are coupled to the corresponding word lines in the other block, so that they are commonly driven in accordance with an output signal from the X-decoder XD.
Referring to
FIGS. 7 and 8
, a read operation, a write operation, and an erase operation of the abovedescribed flash memory FM will be described.
The read operation for the flash memory FM occurs as follows. When a read signal (including a control signal, an address signal, etc.) is supplied from outside of the flash memory FM, a high voltage (e.g., 5 V) is applied to the control gate CG; a low voltage (e.g., 1 V) is applied to the drain D; and a low voltage (e.g., 0 V) is applied to the source S. By detecting the level of the current flowing in the path between the source S and the drain D, the sequence of “1”s and “0”s of the data stored in the memory cell MC is determined. Then, the data read from the memory cell MC is sent to elements outside the flash memory FM, thereby completing the read operation.
The write operation for the flash memory FM occurs as follows. When a control signal, data, and an address signal are supplied from outside of the flash memory FM, a high voltage (e.g., 12 V) is applied to the control gate CG; a high voltage (e.g., 7 V) is applied to the drain D; and a low voltage (e.g., 0 V) is applied to the source S. The hot electrons which are generated in the vicinity of the drain junction are injected to the floating gate FG due to the high voltage applied to the control gate CG. Thereafter, the writing is inactivated and a verify operation takes place. The write operation is complete when the memory cell to which data has been written successfully passes verification. If verification fails, the data is rewritten, followed by another verification. If verification fails after this cycle has been performed a predetermined number of times, a status signal indicating “write error” is returned to elements outside of the flash memory FM.
The erase operation for the flash memory FM occurs as follows. It should be noted that, as mentioned earlier, the erase operation occurs for the entire block, rather than each memory cell therein. When an erase signal (including a control signal and an address signal) are supplied from outside of the flash memory FM, a low voltage (e.g., 0 V) is applied to the control gate CG; a low voltage (e.g., 0 V) is applied to the drain D; and a high voltage (e.g., 12 V) is applied to the source S. With the application of such voltages, a strong electric field is generated between the floating gate FG and the source S, so that the electrons in the floating gate FG can be discharged to the source S due to a tunnel effect. Thereafter, the erasing is inactivated and a verify operation takes place, as in the case of writing. The erase operation is complete when all of the memory cells within the block to be erased successfully pass verification. If verification fails, an erase operation is performed again, followed by another verification. If verification fails after this cycle has been performed a predetermined number of times, a status signal indicating “erase error” is returned to elements outside of the flash memory FM.
In general, the speeds of the read operation, write (including verification) operation, and erase (including verification) operation are of the relationship: “reading speed”>“writing (including verification) speed”>“erasing (including verification) speed”. For example, the read operation may take about 100 ns; the write (including verification) operation may take about 60 &mgr;s; and the erase (including verification) operation may take about 300 ms. Thus, the write and erase operations are several orders of magnitude slower than the read operation. Therefore, it would be very useful in a flash memory to perform a read operation during a write (including verification) operation and an erase (including verification) operation.
FIG. 9
illustrates the block structure of a conventional non-volatile memory device. The conventional non-volatile memory device includes a memory cell array
101
(including blocks
111
,
112
,
113
, and
114
) and a memory cell array
102
(including blocks
115
,
116
,
117
, and
118
). In each of the memory cell arrays
101
and
102
, the corresponding word lines of each block are coupled to a common. The word lines of the memory cell arrays
101
and
102
are commonly driven by X-decoders
131
and
132
, respectively. Source line voltage switching elements
121
, . . . ,
128
selectively apply predetermined voltages to the source lines of the corresponding blocks
111
, . . . , and
118
.
A common sense amplifier
64
is provided for the blocks
111
,
112
,
113
, and
114
and the blocks
115
,
116
,
117
, and
118
. A control circuit
15
includes a read control circuit
151
, a write control circuit
152
, an erase control circuit
153
, a source switch control circuit
154
, a sense amplifier control circuit
155
, and a verify control circuit
156
. The non-volatile memory device further includes an input/output interface circuit
16
for managing the exchange of signals between the control circuit
15
and elements outside of the memory, Y-decoders
171
and
172
, and bit line selection circuits
181
and
182
.
FIG. 10
is a structural diagram illustrating the relationship between the memory cell array
101
(the blocks
111
,
112
,
113
, and
114
) the X-decoder
131
, the Y-decoder
171
, the bit line selection circuit
181
, and the sense amplifier
64
in the conventional non-volatile memory device.
Referring to
FIG. 9
, the operations of the conventional non-volatile memory device will be described.
An erase operation for the block
111
occurs as follows. First, the control circuit
15
switches the source line voltage switching element
121
which is coupled to the block
111
, thereby setting the source voltage in the block
111
at a high voltage (e.g., 12 V). Furthermore, the control circuit
15
applies a low voltage (e.g., 0 V) to the word lines during the application of an erase pulse, and a high voltage (e.g., 5 V) during an erase verify operation, via the X-decoder
131
.
The X-decoder
132
is available during the erase operation. However, sin
Elms Richard
Morrison & Foerster / LLP
Nguyen Van Thu
Sharp Kabushiki Kaisha
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