Phase adjustment circuit

Details Phase adjustment circuit Phase adjustment circuit

1999-11-15

2001-08-07

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S156000, C327S244000

Reexamination Certificate

active

06271696

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a phase adjustment circuit which adjusts delay dispersion that occurs during clock distribution in a logic IC and logic card.
In a conventional logic IC and logic card, a phase adjustment circuit which compares the phases of a reference clock signal supplied from an external device and the phase of a feedback clock signal which shows that delay occurs during internal clock distribution. The phase adjustment circuit controls delay time in the internal clock distribution based on the result of the comparison so that the phase of the feedback clock signal becomes identical to the phase of the reference clock signal.
As the performance of a logic device is enhanced, the clock frequency in a central processing unit and its peripheral devices is increased. However, the clock frequency in an input/output device, a diagnostic device and others is not as high compared to the clock frequency in a central processing unit or its peripheral devices. Therefore, the distribution of a plurality of different of clock signals to one logic IC or one logic card is often required. A plurality of phase adjustment circuits described above is provided for every type of a clock in a single chip.
Referring to
FIG. 4
, a conventional phase adjustment circuit includes three phase-locked loop (PLL) circuits
100
a
to
100
c
, logic devices
20
a
-
1
to
20
a
-n connected to PLL circuit
100
a
, logic devices
20
b
-
1
to
20
b
-n connected to PLL circuit
100
b
and logic devices
20
c
-
1
to
20
c
-n connected to PLL circuit
100
c.
PLL circuit
100
a
includes a variable delay circuit
10
a
, a phase comparing circuit
30
a
and a counter
40
a
. Variable delay circuit
10
a
, to which a clock signal CK
0
having a predetermined cycle is input, delays clock signal CK
0
by a set delay time and outputs it. Phase comparing circuit
30
a
compares the phase of a feedback clock signal CFB
0
, which is output from the variable delay circuit
10
a
and delayed during internal clock distribution, and the phase of a reference clock signal CREF
0
input from an external device. Counter
40
a
increases or decreases its counted value based on the result of the comparison by phase comparing circuit
30
a
. The delay time used in the variable delay circuit
10
a
is set based on a value counted by counter
40
a.
PLL circuit
100
b
includes a variable delay circuit
10
b
, a phase comparing circuit
30
b
and a counter
40
b
. Variable delay circuit
10
b
, to which a clock signal CK
1
having a predetermined cycle is input, delays clock signal CK
1
by a set delay time and outputs it. Phase comparing circuit
30
b
compares the phase of a feedback clock signal CFB
1
, which is output from the variable delay circuit
10
b
and delayed during internal clock distribution, and the phase of a reference clock signal CREF
1
input from an external device. Counter
40
b
increases or decreases its counted value based on the result of the comparison by phase comparing circuit
30
b
. The delay time used in the variable delay circuit
10
b
is set based on a value counted by counter
40
b.
PLL circuit
100
c
includes a variable delay circuit
10
c
, a phase comparing circuit
30
c
and a counter
40
c
. Variable delay circuit
10
c
, to which a clock signal CK
2
having a predetermined cycle is input, delays clock signal CK
2
by a set delay time and outputs it. Phase comparing circuit
30
c
compares the phase of a feedback clock signal CFB
2
, which is output from the variable delay circuit
10
c
and delayed during internal clock distribution, and the phase of a reference clock signal CREF
2
input from an external device. Counter
40
c
increases or decreases its counted value based on the result of comparison by phase comparing circuit
30
c
. The delay time used in the variable delay circuit
10
c
is set based on a value counted by counter
40
c.
Clock signals CK
0
to CK
2
are delayed in variable delay circuits
10
a
to
10
c
, respectively, so that each phase of clock signals CFB
0
to CFB
2
, which are delayed during clock distribution in PLL circuits
100
a
to
100
c
, become identical to each phase of reference clock signals CREF
0
to CREF
2
, respectively. Thus, the time at which the clock signals CK
0
, CK
1
and CK
2
are supplied to logic devices
20
a
-
1
to
20
a
-n,
20
b
-
1
to
20
b
-n and
20
c
-
1
to
20
c
-n, respectively, is adjusted.
However, it is necessary to provide the same number of PLL circuits and reference clock signal input terminals as the number of the phase adjustment circuits when a plurality of phase adjustment circuits are provided in the same chip. This creates a problem because the scale of the hardware becomes large.
While the same reference clock signal is input to the PLL circuits, it is input to the plurality of input terminals and its phase is compared to the phase of a feedback clock signal in the plurality of phase comparing circuits. This creates a problem because a slight error may be produced between the reference clock signals. The error depends on the precision of a circuit which supplies a reference clock signal and dispersion among the characteristics of the phase comparing circuits.
SUMMARY OF THE INVENTION
An object of the invention is to provide a phase adjustment circuit which adjusts the phase of a plurality of different clocks without enlarging the scale of hardware.
According to one aspect of the present invention, a phase adjustment circuit is provided which includes: a plurality of input terminals which input a plurality of clock signals, respectively; a plurality of first elements which input the clock signals, respectively, and adjust the clock signals, respectively; a second element which compares the phase of a reference clock signal and the phase of an output signal from one of the first elements and outputs a compared result; and a third element which inputs the compared result and controls each of the first elements based on the compared result.
According to another aspect of the present invention, a phase adjustment circuit is provided which includes: a plurality of input terminals which input a plurality of clock signals, respectively; a plurality of first elements which input the clock signals, respectively, and oscillate the clock signals, respectively; and a second element which compares the phase of a reference clock signal and the phase of an output signal from one of the first elements and outputs a compared result; wherein the first elements input the compared result and oscillate the clock signals, respectively, based on the compared result.
According to another aspect of the present invention, a method for adjusting the phase between a plurality of clock signals is provided which includes: delaying each of the clock signals by a delay amount; comparing the phase of a reference clock signal and the phase of one of the delayed clock signals which is delayed during the delaying step; and controlling the delay amount based on the compared result which is compared during the comparing step.


REFERENCES:
patent: 5150068 (1992-09-01), Kawashima et al.
patent: 5574756 (1996-11-01), Jeong
patent: 6052007 (2000-04-01), Ono
patent: 3-083415 (1991-04-01), None
patent: 10-301663 (1998-11-01), None

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