Method and system of switching clock signal

Details Method and system of switching clock signal Method and system of switching clock signal

1999-04-27

2001-07-03

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S299000, C327S115000, C327S116000

Reexamination Certificate

active

06255882

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and a system of switching a clock signal and more particularly, to a method and a system of switching the frequency of a clock signal according to a clock-signal switching instruction.
2. Description of the Prior Art
FIG. 1
is a block diagram showing the configuration of a portable computer system that carries out a conventional method of switching a clock signal disclosed in the Japanese Non-Examined Patent Publication No. 5-94226 published in 1993.
As shown in
FIG. 1
, this portable computer system comprises a Central Processing Unit (CPU)
1011
having an internal oscillator
1111
, a reset-signal generator circuit
1012
, a clock-signal selector circuit
1013
, a timing controller circuit
1014
, a clock-signal oscillator
1015
, a frequency-divider circuit
1016
, a trigger circuit
1017
, a latch circuit
1018
, a Random-Access Memory (RAM)
1019
, a Programmable Interrupt Controller (PIC)
1020
, a KeyBoard Controller (KBC)
1021
, and a system timer
1022
.
The CPU
1011
, which controls the whole operation of the computer system, is connected to the timing controller circuit
1014
, the RAM
1019
, the PIC
1020
, the KBC
1021
, and the system timer
1022
through a system bus
1010
. The internal oscillator
1111
of the CPU
1011
generates a dedicated clock signal having a frequency several times as much as that of a clock signal (CLK) supplied through the clock-signal selector circuit
1013
. According to the dedicated clock signal thus generated by the oscillator
1111
, the CPU
1011
operates at a higher speed than that of the case using the clock signal (CLK).
Also, the CPU
101
executes the Basic Input/Output System (BIOS) program called by an application program being executed, thereby judging whether the specific condition for entering the standby mode is satisfied or not. When this condition is satisfied, the CPU
1011
saves the content of the registers (not shown) in the CPU
1011
and executes a halt command for halting the execution of the program. The content of the registers thus saved are stored in the RAM
1019
. After the execution of the halt command, the CPU
1011
advises the timing controller circuit
1014
that the CPU
1011
has entered the standby mode i.e., the halt or stop state.
The reset-signal generator circuit
1012
generates a reset signal (RESET) and supplies the reset signal thus generated to the CPU
1011
. The circuit
1012
sets the reset signal active or inactive under the control of the timing controller circuit
1014
. When the reset signal is turned active, the CPU
1011
enters the reset state. When the reset signal is turned inactive, the CPU
1011
is released from the reset state, in other words, it is returned to the normal operation mode.
The clock-signal selector circuit
1013
selects one of a high-frequency clock signal (CLK
1
) and a low-frequency clock signal (CLK
2
), supplying the selected one (i.e., CLK
1
or CLK
2
) to the CPU
1011
as the operation clock signal (CLK). The circuit
1013
selects normally the high-frequency clock signal (CLK
1
) for high-speed operation of the CPU
1011
. To shift the CPU
1011
from the normal operation mode to the standby mode, the circuit
1013
selects the low-frequency clock signal (CLK
2
) as the operation clock signal (CLK) instead of the high-frequency clock signal (CLK
1
) under the control of the timing controller circuit
1014
.
The high-frequency clock signal (CLK
1
) is generated by the clock oscillator
1015
. The low-frequency clock (CLK
2
) is generated by frequency-dividing the high-frequency clock signal (CLK
1
) by the frequency-divider circuit
1016
.
The timing controller circuit
1014
controls the operation timing of the reset-signal generator circuit
1012
and the clock-signal selector circuit
1013
. In detail, to turn the CPU
1011
from the normal operation mode to the standby mode, the circuit
1014
controls these two circuits
1012
and
1013
in such a way that the operation clock signal (CLK) is switched from the high-frequency clock signal (CLK
1
) to the low-frequency clock signal (CLK
2
) after the operation of the CPU
1011
has entered the reset state. On the other hand, to return the CPU
1011
from the standby mode to the normal operation mode, the circuit
1014
controls these two circuits
1012
and
1013
in such a way that the operation of the CPU
1011
is released from the reset state after the operation clock signal (CLK) has been switched from the low-frequency clock signal (CLK
2
) to the high-frequency clock signal (CLK
1
).
As seen from
FIG. 1
, the timing controller circuit
1014
is equipped with a register
1141
and two delay circuits
1142
and
1143
. The register
1141
is used to set or store a message data issued by the CPU
1011
, where the message data represents the halt or stop state of the CPU
1011
. When the message data is set or stored in the register
1141
, a reset-on signal (RESET-ON) is sent to the reset-signal generator circuit
1012
and the delay circuit
1143
, thereby activating the reset signal (RESET). Thereafter, at the timing delayed by a specific period, a first switch signal (SW
1
) is sent from the delay circuit
1143
to the clock-signal selector circuit
1013
, thereby switching the operation clock signal (CLK) to the low-frequency signal (CLK
2
).
When a trigger signal is inputted from the trigger circuit
1017
into the timing controller circuit
1014
, a second switch signal (SW
2
) is sent from the delay circuit
1142
to the clock-signal selector circuit
1013
, thereby returning the operation clock signal (CLK) to the high-frequency signal (CLK
1
). Then, at the timing delayed by a specific period, a reset-off signal is sent from the delay circuit
1142
to the reset-signal generator circuit
1012
, thereby inactivating the reset signal.
When an interrupt signal (INT) is issued from the PIC
1020
, the trigger circuit
1017
outputs the trigger signal in response to the interrupt signal thus issued. This interrupt signal is sent to the latch circuit
1018
also. The latch circuit
1018
, which is of the transparent type, stores the interrupt signal and supplies it to the CPU
1011
.
The RAM
1019
is used to store the application program executed by the CPU
1011
. On the transition to the standby mode, the content of the registers in the CPU
1011
is also saved and stored in the RAM
1019
.
The PIC
1020
outputs the interrupt signal in response to any hardware interrupt request such as a key-input interrupt request from the keyboard controller
1021
, a timer interrupt request from the system timer
1022
, and so on.
The keyboard controller
1021
outputs a hardware interrupt request according to a key input from a keyboard (not shown), informing the CPU
1011
of issuance of the key-input interrupt request.
The system timer
1022
outputs a hardware interrupt request at regular or constant intervals.
With the conventional method of switching a clock signal shown in
FIG. 1
, as described, above, the operation clock signal (CLK) is switched between the high- and low-frequency signals (CLK
1
and CLK
2
) while the CPU
1011
is kept in the reset state. Then, the CPU
1011
is returned to the normal operation state from the reset state after the switching of the operation clock signal (CLK) is completed. Thus, the operation of the CPU
1011
is not affected by the non-contiguity of phase of the operation clock signal (CLK) caused by its switching operation between the signals CLK
1
and CLK
2
.
Also, the content of the registers in the CPU
1011
is saved and stored in the RAM
1019
on reset of the CPU
1011
, and then, the stored content of the registers is restored to the CPU
1011
on release of the CPU
1011
after the switching of the operation clock signal (CLK) is completed. Thus, the CPU
1011
can restart its operation from the state just before the switching operation of the clock signal (CLK). This means that the operation speed of the CPU
1011
can be switched while ens

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