Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1998-07-01
2001-09-18
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S755090, C324S758010, C324S761010, C324S765010
Reexamination Certificate
active
06292003
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the methodology for testing micro ball grid array (&mgr;BGA) and chip scale package (CSP) integrated circuits (IC's), and more particularly, to an apparatus and method for providing electrical connections between a &mgr;BGA or CSP IC and an IC device tester.
BACKGROUND OF THE INVENTION
An integrated circuit (IC) typically includes an IC chip, which is housed in a plastic, ceramic, or metal “package”. The IC chip includes an integrated circuit formed on a thin wafer of silicon. The package supports and protects the IC chip and provides electrical connections between the integrated circuit and an external circuit or system.
There are several package types, including ball grid arrays (BGA's), pin grid arrays (PGA's), plastic leaded chip carriers (PLCC's), and plastic quad flat packs. Each of the package types is typically available in numerous sizes. The package type selected by an IC manufacturer for a particular IC chip is typically determined by the size/complexity of the IC chip (i.e. the number of input/output terminals), and also in accordance with a customer's requirements.
FIGS. 1
a
and
1
b
show bottom and side sectional views of a typical BGA IC
100
, which includes an IC chip
110
mounted on an upper surface
122
of a package substrate
120
. Electrical connections between bonding pads of IC chip
110
and conductive lines (not shown) formed on substrate
120
are provided by bond wires
150
. A plurality (twenty-five shown) of solder balls (sometimes referred to as solder bumps or solder dots)
140
are electrically connected to the conductive lines and extend from a lower surface
124
of substrate
120
. Electrical signals travel between each solder ball
140
and one bonding pad of IC chip
110
along an associated conductive line and bond wire
150
. A cover
130
, such as a cap or “glob top”, is placed or formed over IC chip
110
and bond wires
150
for protection.
IC manufacturers use an IC testing system to test their IC's before shipping them to customers. An IC testing system typically includes a device tester, a device handler, and an interface structure. The device tester is an expensive piece of computing equipment, which transmits test signals via tester probes to an interface structure. The interface structure transmits signals between the leads of an IC under test and the device tester. The device handler is an expensive precise robot for automatically moving IC's from a storage area to the interface structure and back to the storage area.
FIGS. 2
a
and
2
b
show side and top views of a conventional interface structure
200
, which is used to test BGA IC's. Interface structure
200
includes a disk-shaped printed circuit board (PCB)
210
and a contactor
300
. PCB
210
includes groups of outer vias
220
, which are spaced around the perimeter of PCB
210
. Outer vias
220
receive male tester probes extending from the device tester (not shown). Outer vias
220
are connected by metal traces (conductive lines)
230
to inner sockets
240
located in a central test area. Contactor
300
is mounted over the central test area such that pin terminals (discussed in further detail below) which extend from a lower surface of the contactor
300
are received in the sockets
240
. After a BGA IC is mounted on contactor
300
by the device handler, the device tester transmits test signals through the male tester probes (not shown) to the outer vias
220
, along traces
230
to the sockets, and finally through contactor
300
to the BGA IC under test. Similarly, return signals from the BGA IC are transmitted to the test device through contactor
300
, socket
240
, traces
230
, and outer vias
220
.
FIGS. 3
a
and
3
b
show top and side sectional views of a contactor
300
. Contactor
300
includes a housing
310
and a nesting member
320
movably mounted on housing
310
via support springs
330
. Housing
310
includes lower wall
312
, side walls
314
extending upward around the periphery of lower wall
312
, and spring mounts
316
for receiving one end of support springs
330
. A peripheral edge of nesting member
320
is surrounded by outer side walls
314
of housing
310
, thereby limiting horizontal movement of nesting member
320
. However, a small gap G
1
is provided between nesting member
320
and side walls
314
to allow vertical movement. Nesting member
320
includes a plate portion
322
positioned over the lower wall
312
of housing
310
, and raised alignment walls
323
located at two corners of plate portion
322
which define a receiving area for BGA IC
100
(indicated in dashed lines). Plate portion
322
includes an indented area
324
having an upper surface
325
, a lower surface
326
, and a plurality of through-holes
328
. Contactor
300
also includes a plurality of C-spring contacts
340
each having a C-shaped spring portion
342
. Each spring contact
340
includes a contact portion
344
which extends through one of the through-holes
328
of nesting member
320
, and a pin terminal
346
which extends through lower wall
312
of housing
310
. When contactor
300
is mounted onto PCB
210
, pin terminals
346
are received in sockets
240
formed in PCB
210
.
While C-spring contacts
340
have been shown in
FIG. 3
b
, several alternative methodologies exist for providing electrical contact with BGA IC
100
(indicated by dashed lines). A few of the more common methodologies include an S-spring contact
347
, as shown in
FIG. 3
c
, a fuzz button contact
348
, as shown in
FIG. 3
d
, and a pogo pin contact, as shown in
FIG. 3
e
. However, all conventional methodologies share similar performance characteristics and issues.
Operation of conventional interface structure
200
is described with reference to
FIGS. 4
a
and
4
b
. As shown in
FIG. 4
a
, a device handler (not shown) places BGA IC
100
(shown in silhouette) onto nesting member
320
with solder balls
140
extending into indented area
324
. BGA IC
100
is aligned on nesting member
320
by contact between the peripheral edge of BGA IC
100
and raised alignment walls
323
of nesting member
320
. This alignment is intended to position solder balls
140
over the contact portions
344
of spring contacts
340
. Subsequently, as shown in
FIG. 4
b
, the device handler presses BGA IC
100
downward (in the direction indicated by arrow Z) against the force exerted by support springs
330
. As nesting member
320
is displaced downward, solder balls
140
move toward and abut contact portions
344
. Further downward force is absorbed by the spring portion of spring contacts
340
. When BGA IC
100
is properly aligned, electrical signals are then transmitted between PCB
210
and BGA IC
100
through contact between solder balls
140
and contact portions
344
of spring contacts
340
. The device handler then removes BGA IC
100
, and nesting member
320
is biased into its original position by support springs
330
.
Several problems are associated with conventional interface structure
200
, and in particular, to conventional contactor
300
.
First, contactor
300
is expensive (approximately $500 or more) and also very fragile. Pin terminals
346
of spring contacts
340
are often bent or damaged when contactor
300
is mounted to PCB
210
. Straightening or replacing bent pin terminals
346
is extremely time-consuming, and therefore IC testing system operators often simply discard damaged contactors. Further, due to their simple construction, spring contacts
340
typically weaken and fail after a relatively low number of test procedures. As a result, device testing using conventional interface structures is expensive and often time-consuming.
A second problem associated with conventional interface structure
200
is described with reference to
FIG. 4
c
. Nesting member
320
can become misaligned due to temperature variations. Interface structures are typically mounted on device testers at room temperature. Subsequent testing procedures are often
Fredrickson Toby Alan
Hornchek Eric D.
Bever Patrick T.
Deb Anjan K
Metjahic Safet
Xilinx , Inc.
Young Edel
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