Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-05-28
2001-03-20
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S158000, C327S159000, C327S276000, C327S277000
Reexamination Certificate
active
06204705
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the field of delay locked loops, and more particularly to a delay locked loop with an improved shunt-capacitor delay cell and with a capability to compensate for aliased signals.
BACKGROUND OF THE INVENTION
Conventional delay locked loops (DLLs) include delay cells with topologies that are based on either the “current-starved” approach or on the shunt-capacitor approach, as described below and in Mark Johnson and Edwin Hudson,
A Variable Delay Line PLL for CPU-Coprocessor Synchronization
, IEEE Journal of Solid State Circuits, Volume 23, No. 5, pp. 1218-1223 (October 1988).
FIG. 1
a
is a schematic circuit diagram of a conventional delay cell
100
that employs the current-starved approach. Specifically, the delay cell
100
includes an inverter
105
formed by transistors
107
and
109
, a current mirror formed by the p-channel transistors
110
and
115
, and n-channel transistors
120
and
125
. The value of a control signal “Vcontrol” determines the current flow in the n-channel transistor
120
and the n-channel transistor
125
. At lower values for Vcontrol, the current flow in the n-channel transistor
125
(or n-channel transistor
120
) is low. As the value of Vcontrol increases, the current in the n-channel transistor
125
increases. A low current value provided by n-channel transistor
125
limits the value of I
DS(109)
which is the drain-to-source current of n-channel transistor
109
. As the I
DS(109)
value decreases, the switching speed of inverter
105
decreases, thereby adding delay when generating the output signal V
out
from the input signal V
in
. In order to increase the delay provide by the current-starved delay element
100
to the input signal V
in
, the value of control signal Vcontrol is, therefore, decreased.
Conversely, as the I
DS(109)
value increases, the switching speed of inverter
105
increases, thereby decreasing the delay when generating the output signal V
out
from the input signal V
in
. In order to decrease the delay provided by delay element
100
to the input signal V
in
, the value of control signal Vcontrol is, therefore, increased.
One disadvantage of the current-starved approach is that the current values must be precise and that the devices must match in the current-starved delay element
100
. Furthermore, if a short delay is to be provided to the input signal V
in
by the delay element
100
, then the operating current typically has a high value. In addition, to compensate for process, temperature, and voltage supply variations, the sizes of the current mirrors, which consist of the p-channel transistors
110
and
115
and the n-channel transistors
120
and
125
in delay cell
100
, are large in value. These characteristics disadvantageously lead to high power requirements and large die sizes. Other drawbacks for the delay cell
100
include low immunity to noise and the requirement of precise wiring to minimize noise interference. For example, conductors are preferably not crossed in the delay cell
100
in order to decrease noise interference.
FIG. 1
b
is a schematic circuit diagram of a conventional delay cells
150
that employs the shunt-capacitor approach. Specifically, the delay cell
150
includes an inverter
160
, an n-channel transistor
165
coupled to the inverter
160
output, and a capacitor
170
coupled the n-channel transistor
165
. The inverter
160
receives the input signal V
in
and generates the output signal V
out
. The delay cell
150
also includes an inverter
175
, an n-channel transistor
180
coupled to the inverter
175
output, and a capacitor
185
coupled to the n-channel transistor
180
.
The control signal Vcontrol controls the amount of resistance provided by the n-channel transistors
165
and
180
. If, for example, the control signal Vcontrol is at a low level, then the resistance provided by the n-channel resistor
165
between the node
190
and the capacitor
170
is at a high value. An open circuit is effectively present between the node
190
and the capacitor
170
, and the capacitor
170
is, therefore, not coupled as a capacitive load to the inverter
160
output. Therefore, the switching speed of inverter
160
is at a faster rate, thereby decreasing the delay of the input signal V
in
.
If, however, the control signal Vcontrol is at a high level, then the resistance provided by the n-channel resistor
165
between the node
190
and the capacitor
170
is at a lower value. The n-channel transistor
165
, therefore, allows the node
190
to be coupled to the capacitor
170
. Since the capacitor
170
acts as a capacitive load on the inverter
160
output, the switching speed of inverter
160
is at a slower rate. Thus, the delay is increased for the input signal V
in
.
However, the effectiveness of the delay control provided by the n-channel transistor
165
(or n-channel transistor
180
) is limited for the following reason. Due to the body-effect, the threshold voltage required for turning on the n-channel transistor
165
(or n-channel transistor
180
) may rise to, for example, 1.0 volts to 1.2 volts. A further disadvantage of the shunt-capacitor based delay cell in
FIG. 1
b
is that if the capacitor
170
(or capacitor
185
) is implemented by a p-type device, the capacitor
170
will be referenced to the positive voltage source VDD instead of the ground voltage VSS. As a result, when the output signal V
out
is switching from a low level to a high level, the capacitor
170
will be bootstrapped above the VDD level, and this condition may cause a soft breakdown for the capacitor
170
. Therefore, there is a need for an improved delay cell that overcomes the aforementioned problems of conventional approaches.
Conventional delay locked loops also include phase detectors that are commonly unable to distinguish aliased signals from fundamental signals. An aliased signal occurs when the feedback clock signal in the delay locked loop is lagging a reference clock signal (received by the DLL) by more than one cycle and may often cause the DLL to lock to an inappropriate edge of the reference clock signal Refclk. Therefore, there is a need for a delay locked loop that can compensate for aliased signals, thereby leading to improved DLL performance.
SUMMARY OF THE INVENTION
The present invention provides a delay locked loop including a delay circuit capable of generating an output clock signal and further capable of generating a GATE signal in response to an aliased condition. A phase detector is coupled to the delay circuit and is capable of comparing a phase difference between a reference clock signal and the output clock signal from the delay circuit and generating a pump up signal if the output clock signal is lagging the reference clock signal. The phase detector is capable of generating a pump down signal if the output clock signal is leading the reference clock signal. A charge pump is coupled to the phase detector and is capable of generating a control voltage for controlling the delay provided to the output clock signal and capable of pulling up the control voltage in response to the GATE signal to increase the speed of the output clock signal.
In addition to overcoming the disadvantages of conventional approaches, the present invention can detect the occurrence of aliased signals and accordingly provide a delay locked loop with an improved phase locking capability. The present invention can also advantageously be implemented by use of a single polycrystalline CMOS process which is a relatively inexpensive and accurate process.
The phase detector in the delay locked loop further provides symmetrical output signals for pumping up or pumping down the charge pump. Furthermore, the phase detector has good resolution, since the overlap between the pump up signal and the pump down signal from the charge pump permits detection of phase differences of as low as approximately fifty (50) pico-seconds. Furthermore, the phase detector can continuously determine phase differences between reference clock signal
Dinh Paul
Fenwick & West LLP
Kendin Communications, Inc.
Wells Kenneth B.
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