Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing
Utility Patent
1998-07-29
2001-01-02
Lee, Thomas C. (Department: 2782)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Product assembly or manufacturing
C700S121000
Utility Patent
active
06169931
ABSTRACT:
BACKGROUND
This invention relates generally to Chemical Mechanical Polishing (CMP) processes for planarizing and polishing the substrates used in the manufacture of integrated circuits. More particularly, the invention is a method and system for modeling, predicting and optimizing the performance of the CMP polishing medium, called polishing pads, and thus predicting pad wear and extending pad life. The present method and system integrates uniformity, planarity, and pad conditioning and wear models to predict CMP polishing pad performance and then uses the resulting predictions to optimize CMP polishing pad performance and extend pad life.
Chemical mechanical polishing (CMP) is a method of removing material from the surface of semiconductor wafers and other types of substrates used in the manufacture of integrated circuits. For the purposes of simplifying the discussion, the term wafer is used to denote the workpiece undergoing the CMP process. However, other types of substrates that utilize CMP processes can be used interchangeably with the term wafer. In the CMP process, the semiconductor wafer is placed on a wafer carrier and pressed face-down on a rotating platen holding a polishing pad. The polishing pad typically has two layers: a relatively stiff upper pad and a relatively soft base pad. A slurry with an abrasive material (for example, silica particles of size 10-200 nm) held in suspension is dripped onto the rotating platen and pad during polishing. The carrier and platen rotate at variable speeds, typically on the order of 30 rpm. The number of wafers that may be simultaneously polished varies: single-wafer, dual-wafer, and five-headed polishing systems currently exist.
The CMP process removes material at the surface of the wafer through this combination of mechanical and chemical action. The CMP process is performed at various stages in the fabrication of devices on a substrate. The planarization of dielectric (silicon dioxide) layers between multilevel metallization steps is one common application. CMP is used to planarize these interlevel dielectric (ILD) materials, which have patterns on them that result from being deposited over patterned metal lines. CMP is also used to polish metal films such as tungsten and copper by completely removing them except for that which remains in trenches purposely pre-etched in the underlying ILD. The goal of the CMP process is to uniformly remove material from the surface of the wafer to achieve wafer-scale uniformity. In silicon dioxide, small features are also removed to achieve feature-scale planarity. In polishing metal films, the CMP process attempts to preserve small features that are pre-etched in the underlying ILD.
Because the CMP polishing pad is a major component in the CMP process, analyzing its changing properties and characteristics throughout the polishing process is especially important in understanding and predicting uniformity and planarity of the polished wafer. Since the CMP process includes mechanical abrasion of the surface, the polishing pad wears rapidly. This is often referred to as pad degradation, which corresponds to the gradual decay of removal rate of the material from the wafer surface. The decay in removal rate is due to the decrease in roughness of the abrasive surface of the pad as the pad degrades with use. In order to minimize pad degradation, pad conditioning is usually employed whereby the abrasive surface of the pad is restored, either by mechanical damage to the surface or removal of a thin surface layer. Although this helps to roughen the pad and temporarily restore the material removal rate, pad conditioning decreases the thickness of the pad, which in turn decreases pad life. Two key physical properties affect pad life: the thickness of the top pad and the compressibility of the base pad, both of which change with use. Repeated use and conditioning reduces the top pad thickness and repeated cyclical loading reduces the base pad compressibility. Pad thinning results in a reduced planarization rate, which ultimately ends pad life.
Since the pad degrades over time as it is used for polishing and the removal rate of the semiconductor material varies based in part on pad age and wear, wafer-to-wafer uniformity is difficult to predict. It is even difficult to achieve and maintain uniform material removal within the same wafer because the polishing pad removal rate may not be constant over the wafer due to changes in pad thickness and roughness. As the pad is conditioned as part of the CMP process, the top layer of the pad that contacts the wafer is roughened, meaning material is removed and the pad becomes thinner and correspondingly less stiff. The softer base pad layer of the pad is compressed due to the downforce of the wafer and also becomes thinner over time. Changes in the pad roughness and thickness may also be due in part to the differences between the polishing action or rate at the center and edge of the wafer that may arise due to a number of factors including wafer asymmetry, non-constant relative pad velocity from the edge of the wafer to the center, non-uniform slurry and by-product transport under the wafer, wafer bowing due to pressure, or machine drift in time of any of these parameters.
Since CMP is now the preferred method of removing material from the surface of semiconductor wafers and other types of substrates used in the manufacture of integrated circuits, efforts are continually being made to optimize CMP processes. Meaningful CMP optimization must consider all factors that are significant in affecting the overall quality of CMP performance including uniformity, planarity, and pad conditioning and wear. Historically, uniformity has played the dominant role in modeling for CMP optimization. Although equally important, planarity has played a secondary role in such optimization. Modeling systems to simulate and predict the removal rate of features on semiconductor wafer surfaces polishing to achieve wafer-scale uniformity during the CMP process presently exist. There also exist modeling systems to simulate and predict the removal of small features to achieve feature-scale planarity during the CMP process. Even though pad conditioning and wear is an important CMP performance metric, accurately simulating and predicting pad degradation over time as not been included in prediction and optimization systems for CMP processes. No present wafer-scale uniformity or feature scale uniformity modeling system incorporates a pad conditioning and wear model that accurately simulates the physical properties that influence pad degradation. Therefore, there is no present system that uses wafer-scale uniformity and feature-scale planarity models along with a pad conditioning and wear model to improve wafer-scale uniformity and feature-scale planarity predictions and then utilizes those predictions to optimize the CMP process while achieving improvements in semiconductor wafer uniformity and planarity. In addition, no present system exists that use a pad conditioning and wear model in conjunction with the wafer-scale uniformity and feature-scale planarity models to predict pad performance and extend polishing pad life, thereby increasing the number of semiconductor wafers or other types of substrates that can be chemically-mechanically polished with one polish pad.
SUMMARY
The present invention is a method and system that uses wafer-scale uniformity and feature-scale planarity models along with a pad conditioning and wear model to improve wafer-scale uniformity and feature-scale planarity predictions. It then utilizes those predictions to optimize the CMP process to achieve improvements in semiconductor wafer uniformity and planarity. Use of the pad conditioning and wear model in conjunction with the wafer-scale uniformity and feature-scale planarity models can be used to predict pad performance and extend polishing pad life. Extending pad life results in an increase in the number of semiconductor wafers or other types of substrates that can be polished with one polishing pad. This can resul
Lee Thomas C.
Patel Nitin
Southwest Research Institute
Taylor Russell & Russell P.C.
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