Semiconductor device manufacturing: process – Including control responsive to sensed condition – Optical characteristic sensed
Reexamination Certificate
1999-06-30
2001-01-16
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
Optical characteristic sensed
Reexamination Certificate
active
06174739
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the manufacture of high performance semiconductor devices. More particularly, this invention relates to a method of monitoring the profiles of filled or unfilled trenches or vias during the manufacturing process. Even more particularly, this invention relates to a non-destructive in-situ method of monitoring the profiles of filled or unfilled trenches or vias during the manufacturing process.
2. Discussion of the Related Art
The increased demand for higher performance semiconductor devices has required more complex process technologies and materials to be utilized in the manufacture of semiconductor integrated devices. One way to increase the performance of a semiconductor integrated device such as a microprocessor is to reduce the dimensions of the elements that make up the microprocessor. The reduced dimensions have increased the performance of the microprocessor significantly to the point that the interconnect structure of the microprocessor has proved to be a roadblock to a further increase in performance. One reason for this is because as increased performance is required, more transistors need to be manufactured in the semiconductor-integrated device. These added transistors require more wiring in the interconnect structure. The increased density of the wiring can result in a decrease in the microprocessor performance for various reasons including such phenomena as a decrease in performance due to RC delays. In order to support the increased transistors and to counteract the degradation in performance, additional metal layers in which interconnects are formed are manufactured in order to separate the wiring in both the vertical and horizontal directions. As can be appreciated, each metal layer requires an interconnect structure made up of vias (metal connections between layers) and wires (metal connections in a layer).
These requirements have necessitated the development of novel approaches in the method of forming interconnections that not only integrate fine geometry definition but also can be efficiently implemented into the manufacturing process.
One method of forming a via or a trench in which a wire is formed is known as the damascene process, which comprises forming a hole or trench in an interlayer dielectric material by a masking and etching technique and by a subsequent filling of the hole or trench with a conductive material. The damascene process is a useful method for attaining the fine geometry metallization required for advanced semiconductor devices. A dual damascene process is a two-step sequential mask/etch process to form a two level structure such as a via connected to a metal line above the via.
However, the dimensions of the vias and the trenches have been reduced to the point that conventional inspection devices cannot determine if the openings for the vias and trenches are fully “open” or if the quality of the electrical contacts that will be formed in the openings will be adequate for the purpose for which they are intended. For example, FIGS.
3
A-
3
E show various conditions of openings possible after an etch process to form an opening in a layer of interlayer dielectric.
FIG. 3A
shows the ideal condition of an opening and
FIGS. 3B through 3E
show conditions of openings that begin with conditions that are less than ideal but acceptable to conditions that are unacceptable. Because conventional inspection techniques cannot determine the condition of the openings, the manufacturing process continues and if there are unacceptable conditions they will not be discovered until the wafers have been completely processed. As can be appreciated, this results in a large waste of resources.
Therefore, what is needed is a nondestructive method of inspecting the condition of openings formed in layers of interlayer dielectric and alternatively, a nondestructive method of inspecting the condition of metal structures formed in the openings formed in layers of interlayer dielectric.
SUMMARY OF THE INVENTION
According to the present invention, the foregoing and other objects and advantages are obtained by a method of manufacturing in which filled or unfilled via and trench profiles are nondestructively monitored during the manufacturing process.
In accordance with an aspect of the invention, a layer of an interlayer dielectric is formed on a surface of a semiconductor device, at least one opening is formed in the layer of interlayer dielectric and the profile of the at least one opening is determined.
In accordance with another aspect of the invention, it is determined if the profile of the at least one opening is acceptable. If the profile is acceptable, the processing is continued. If the profile is not acceptable, the profile is analyzed and the manufacturing recipe is modified.
In accordance with another aspect of the invention, the at least one opening is filled with a metal to form a metal structure and the profile of the metal structure is determined.
In accordance with still another aspect of the invention, it is determined if the profile of the metal structure is acceptable. If the profile is acceptable, the processing is continued. If the profile is not acceptable, the profile is analyzed and the manufacturing recipe is modified.
In accordance with another aspect of the invention, the profiles of either the opening or the metal structure is accomplished by scanning the opening or the metal structure with overlapped excitation pulses that form a temporally varying excitation radiation field causing a time-dependent ripple to be generated that is irradiated by a probe pulse that diffracts into at least two signal beams. One of the diffracted signal beams is detected and digitized to produce a digitized waveform signal that is analyzed in a CPU to obtain a frequency of the digitized waveform signal and is compared to characterization waveforms stored in a database to determine the profile of the selected filled or unfilled via or trench.
The described methods thus provide a nondestructive method of monitoring the profiles of filled or unfilled trenches and vias during the manufacturing process. This results in less scrap and less waste of valuable resources.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, embodiments of this invention are shown and described simply by way of illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications in various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.
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Chang & Sza, Editors, ULSI Technology, 1996, McGraw-Hill, pp. 627-629.
Advanced Micro Devices , Inc.
Bowers Charles
Nelson H. Donald
Pert Evan
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