Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
1997-12-12
2001-04-10
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C438S401000
Reexamination Certificate
active
06215197
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to an alignment mark used for superimpose the first electrode on an element active region with high accuracy in a semiconductor device with trench isolation structure.
2. Description of the Background Art
FIGS. 45
to
51
are cross sections showing steps for manufacturing a semiconductor device with trench isolation structure in the background art. The manufacturing method will be discussed below, with reference to these figures.
First, a silicon oxide film
3
and a silicon nitride film
4
are formed on a silicon substrate
1
in this order. With a field mask, the silicon oxide film
3
and the silicon nitride film
4
are patterned. The resist used for the patterning is removed and a dry etching of 2000 to 4000 Å is performed to form trenches
10
(
10
A to
10
C) having a predetermined depth in the silicon substrate
1
as shown in FIG.
45
. Specifically, relatively wide trenches
10
A are formed in an alignment mark area
11
A, narrow trenches
10
B are formed in a memory cell area
11
B and wide trenches
10
C are formed in a peripheral circuit area
11
C. Thus, the trenches
10
A and
10
C in the alignment mark area
11
A and the peripheral circuit area
11
C are formed in a loose pattern and the trenches
10
B in the memory cell
11
B are formed in a dense pattern.
Subsequently, as shown in
FIG. 46
, side surfaces and bottom surfaces of the trenches
10
A to
10
C are oxidized by thermal oxidation and then a silicon oxide film
2
is deposited by CVD. While the silicon oxide film
2
on the wide trenches
10
A and
10
C is as thick as the deposited film, the silicon oxide film
2
on the narrow trench
10
B is thicker than the deposited film since the insulating film is buried into the narrow trenches at an early stage of deposition. In other words, there is a difference in thickness between the silicon oxide film
2
on the trenches
10
B and that on the trenches
10
A and
10
C. The difference is referred to as a thickness difference of silicon oxide film on trench.
In order to reduce the thickness difference of silicon oxide film on trench, a resist pattern
5
is formed only on the buried silicon oxide films
2
on the wide trenches
10
A and
10
C with a mask which is different from the field mask, as shown in
FIG. 47
, and then a dry etching is performed to remove part of the silicon oxide film which is convex. Hereinafter, this step is referred to as preetching in some cases.
After removing the resist pattern
5
, the whole surface is entirely polished by CMP (Chemical Mechanical Polishing), as shown in
FIG. 48
, to remove the silicon oxide film on the silicon nitride film
4
and part of the silicon oxide film on the trenches
10
A to
10
C.
Next, as shown in
FIG. 49
, the silicon nitride film
4
is removed with phosphoric acid and the silicon oxide film
3
is removed with hydrofluoric acid, to form a buried silicon film
2
A in the alignment mark area
11
A, a buried silicon film
2
B in the memory cell area
11
B and a buried silicon film
2
C in the peripheral circuit area
11
C which constitute a trench isolation structure.
Subsequently, as shown in
FIG. 50
, a gate oxide film
6
is formed by thermal oxidation and a polysilicon film
7
doped with phosphorus and a tungsten silicide film
8
are formed on the gate oxide film
6
in this order.
Next, as shown in
FIG. 51
, with the buried silicon oxide film
2
A (alignment mark) which is formed on the step of forming the isolation structure in the alignment mark area
11
A, a pattern for superimposing a gate electrode on an isolation region is formed by photolithography, and gate electrodes
14
are formed in the memory cell area
11
B and the peripheral circuit area
11
C through partially removing part of the tungsten silicide film
8
and the polysilicon film
7
by dry etching.
The semiconductor device and the method for manufacturing the same in the background art as discussed above have the following problem.
In patterning of the gate electrode
14
made of the first electrode material, to form a pattern in a predetermined portion of the active region, it is necessary to superimpose it on the active region. For this superimposition, the alignment mark
2
A which is formed in the step of forming the isolation structure in the alignment mark area
11
A is used.
In the semiconductor device with trench isolation structure, however, it is difficult to detect the mark by the height difference of surface since there is little difference in height of the alignment mark. Moreover, since a silicide film which is part of the gate electrode material reflects light (monochromatic light (wavelength: 633 m)) and white light (wavelength: 530 to 800 m), not passing light, it is also difficult to detect the mark by image recognition.
With difficulties of the mark detection, the accuracy of alignment becomes lower and therefore it disadvantageously becomes impossible to achieve accurate superimposition of gate masks for formation of gate electrode.
SUMMARY OF THE INVENTION
The present invention is directed to a semiconductor device in which semiconductor elements are isolated with a trench isolation structure. According to a first aspect of the present invention, the semiconductor device comprises: a semiconductor substrate; an alignment mark area provided on the semiconductor substrate, having a first trench in an upper portion of the semiconductor substrate and an alignment insulating film provided in the first trench; and an element formation area provided on the semiconductor substrate, having an isolation insulating film used for isolating a plurality of semiconductor elements, the isolation insulating film filling a second trench provided in the upper portion of the semiconductor substrate. In the semiconductor device of the first aspect, the alignment insulating film has a height difference with the highest portion of the alignment insulating film being higher than a surface of the semiconductor substrate and a surface of the lowest portion being lower than the surface of the semiconductor substrate.
According to a second aspect of the present invention, the semiconductor device comprises: a semiconductor substrate; an alignment mark area provided on the semiconductor substrate, having a first trench in an upper portion of the semiconductor substrate and an alignment insulating film provided in the first trench, the alignment insulating film being formed in a peripheral portion other than a center portion of the first trench; and an element formation area provided on the semiconductor substrate, having an isolation insulating film used for isolating a plurality of semiconductor elements, the isolation insulating film filling a second trench provided in the upper portion of the semiconductor substrate, a bottom surface of the center portion of the first trench being formed deeper than the a bottom surface of the second trench. In the semiconductor device of the second aspect, the alignment insulating film has a height difference between the highest portion and the bottom surface of the center portion.
According to a third aspect of the present invention, in the semiconductor device, the semiconductor substrate includes an SOI substrate having an underlying substrate, a buried insulating film formed on the underlying substrate and an SOI layer formed on the buried insulating film, and the first and second trenches penetrate the SOI layer and the center portion of the first trench is formed by further removing a part of the buried insulating film.
According to a fourth aspect of the present invention, the semiconductor device further comprises: a control electrode provided on the element formation area, for controlling a device operation; an interlayer insulating film provided on the semiconductor substrate including the control electrode and a portion above the first trench; a first through hole penetrating the interlayer insulati
Loke Steven
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Vu Hung Kim
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