Semiconductor memory device having multi-bank and global...

Details Semiconductor memory device having multi-bank and global... Semiconductor memory device having multi-bank and global...

2000-03-29

2001-08-21

Phan, Trong (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

Reexamination Certificate

active

06278647

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device having a multi-bank, each bank having a plurality of local data buses connected to global data bus.
2. Description of the Related Art
FIG. 7
is a schematic block diagram showing a configuration of a prior art synchronous DRAM with banks
0
and
1
of the same architecture.
For example, when contents of memory cells C
1
and C
2
in a memory cell array
10
of the bank
0
are read out, a word line WL is activated by a row decoder
11
, whereby a plurality of memory cells coupled to the word line WL are conducted to bit line pairs of respective columns and very small changes in voltage between the bit line pairs are amplified by sense amplifier rows
31
and
32
arranged at both sides of a memory cell block
21
including the word line WL.
On the other hand, block switches BS
01
and BS
02
corresponding to selected memory cell block
21
are switched on by a block decoder
13
, thereby local data buses LDB
01
and LDB
02
routed in (above and along) the sense amplifier rows
31
and
32
are conducted to global data buses GDB
1
and GDB
0
, respectively.
Then, a column selection line CSL is activated by a column decoder
12
, thereby column switches CS
20
to CS
24
are switched on and voltages on bit lines connected to the column switches CS
20
to CS
24
are taken out onto local data buses LDB
00
to LDB
04
. Since block switches BS
00
, BS
03
, BS
04
and BS
01
to BS
14
are off except the block switches BS
01
and BS
02
, voltages on the buses DB
01
and LB
02
are transmitted to the global data buses GDB
1
and GDB
0
, then the voltages are amplified in a read/write amplifier
40
, next the amplified voltages are converted to external voltages in an I/O data buffer
41
and taken out to the outside as DATA.
In a write operation, DATA provided from the exterior is converted into an internal voltage in the I/O data buffer
41
, amplified in the read/write amplifier
40
, and transmitted in a reverse direction to that in the read operation to write DATA into the selected memory cell.
Since a memory block is selected with an address in binary number, the number of the memory blocks is an even number “N”, and the number of sense amplifier rows sandwiching memory blocks is an odd number (N +1). Further, since voltages are transmitted to different global data buses from local data buses routed in (above and along) sense amplifier rows sandwiching the selected block, the local data buses LDBOO to LDBO
4
are alternately coupled to the global data buses GDB
0
and GDB
1
.
Under such conditions, in the prior art, the same pattern has been repeated in laying out on a chip using the same pattern data for each bank to form a plurality of banks.
For this reason, the numbers of local data buses connected to the buses GBD
0
and GBD
1
are different from each other, and in a case of
FIG. 7
, the bus GBD
0
has a heavier load than that of the bus GBD
1
. The operating speeds of read and write are determined by one of the buses whichever has a heavier load, which is a cause for slowing down the operating speed.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor memory device that can attain a higher operating speed by eliminating the difference in load between data buses.
In the present invention, there is provided a semiconductor memory device comprising: an even number of banks; each bank including: an odd number, equal to or more than three, of sense amplifier rows; a plurality of local data buses disposed along respective sense amplifier rows; and a plurality of memory cell blocks arranged between adjacent two of the sense amplifier rows, each memory cell block having memory cells arranged in rows and columns, and first and second global data buses, commonly used for the banks, coupled to the local data buses in such a way that two memory cells in a selected memory cell block are simultaneously accessed through two adjacent local data buses sandwiching the selected memory cell block and through the first and second global data buses, wherein the number of local data buses coupled to the first global data bus is equal to the number of local data buses coupled to the second global data bus.
With the present invention, since the number of local data buses coupled to the first global data bus and the number of local data buses coupled to the second global data bus are equal, no imbalance in load between the global data buses arises, thereby improving an operating speed as compared with a prior art case with an imbalance in load.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.


REFERENCES:
patent: 5822261 (1998-10-01), Suh
patent: 5838604 (1998-11-01), Tsuboi et al.
patent: 6151265 (2000-11-01), Takita et al.
patent: 6166989 (2000-12-01), Hamamoto et al.

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