Semiconductor device including a plurality of...

Details Semiconductor device including a plurality of... Semiconductor device including a plurality of...

1999-07-15

2001-09-11

Quach, T. N. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S773000, C257S775000

Reexamination Certificate

active

06288447

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a CMOS logic circuit element, a semiconductor device, manufacturing method thereof and to a method of designing a semiconductor circuit used in the manufacturing method. More specifically, the present invention relates to a CMOS logic circuit device, a semiconductor device, manufacturing method thereof and a method of designing a semiconductor circuit used in the manufacturing method enabling higher speed of operation and reduced power consumption and preventing degradation of electrical characteristics, even when the devices are miniaturized.
2. Description of the Background Art
Higher degree of miniaturization, higher speed of operation and lower power consumption have been increasingly desired in semiconductor devices such as represented by CMOS logic circuit devices and DRAMs (Dynamic Random Access Memory). To meet such demands, developments have been made in improving transistor performance, reduction in parasitic capacitance of interconnection layers and reduction of line resistance.
FIG. 19
is a schematic cross section representing a multi-layered interconnection structure of a semiconductor device related to the present invention. Referring to
FIG. 19
, in the semiconductor device, on a first interlayer insulating film
146
a
, a first interconnection
145
a
of aluminum is formed. On the first interconnection
145
a
, second interconnections
145
b
to
145
d
of aluminum are formed with a second interlayer insulating film
146
b
interposed. On second interconnections
145
b
to
145
d
, a third interconnection
145
e
is formed with a second interlayer insulating film
146
b
. On the third interconnection
145
e
, a third interlayer insulating film
146
c
is formed. Here, second interconnections
145
b
to
145
d
are formed to extend in a direction approximately orthogonal to the direction of extension of the first and third interconnections
145
a
and
145
e.
Referring to
FIG. 19
, as the semiconductor devices have been miniaturized, a space S between interconnections becomes smaller. As the space S between interconnections becomes smaller, total parasitic capacitance Ctot (hereinafter referred to as total capacitance) of interconnection
145
c
has been increasing. Here, the total capacitance Ctot is represented as the total sum of parasitic capacitance Cc formed between interconnections
145
b
and
145
d
adjacent in horizontal direction, parasitic capacitance Ctop formed between interconnections
145
e
and
145
c
, and parasitic capacitance Cbot formed between interconnections
145
a
and
145
c
. When the space S between interconnections is made small, the ratio of parasitic capacitance Cc with respect to total capacitance Ctot attains as high as about 80%.
Therefore, conventionally, in order to reduce the parasitic capacitance Cc between interconnections in the horizontal direction, a proposal has been made to place an insulator having relatively low dielectric constant such as a silicon oxide film to which fluorine added (SiOF) between adjacent interconnections, so as to reduce parasitic capacitance Cc in the horizontal direction.
The insulator having low dielectric constant such as SiOF, however, involves larger amount of leakage current as compared with the conventionally used silicon oxide film and, further, it suffers from the problem of high reactivity with the material such as aluminum of interconnections
145
a
to
145
e
. Accordingly, a multi-layered interconnection structure of a semiconductor device such as shown in
FIG. 20
has been proposed.
FIG. 20
is a schematic cross section showing another example of the multi-layered interconnection structure of a semiconductor device related to the present invention. Referring to
FIG. 20
, the semiconductor device basically has the similar structure as the semiconductor device of FIG.
19
. In the semiconductor device shown in
FIG. 20
, however, surfaces of second interconnections
145
b
to
145
d
are covered by portions
157
a
to
157
c
of the interlayer insulating film, which are parts of the conventional interlayer insulating film
146
b
of silicon oxide. Insulators
156
a
to
156
d
having low dielectric constant such as SiOF, having lower dielectric constant than silicon oxide film constituting the interlayer insulating film
146
b
, are arranged between interconnections
145
b
to
145
d
. On second interlayer insulating film
146
b
and insulators
156
a
to
156
d
of low dielectric constant, an interlayer insulating film
146
d
of silicon oxide is formed.
In this manner, as insulators
156
a
to
156
d
having low dielectric constant are arranged between interconnections
145
b
to
145
d
, parasitic capacitance Cc in the horizontal direction of interconnection
145
c
can be effectively reduced. Further, as portions
157
a
to
157
c
of interlayer insulating film formed of silicon oxide are formed between interconnections
145
b
to
145
d
and insulators
156
a
to
156
d
of low dielectric constant, direct contact between interconnections
145
b
to
145
d
with insulators
156
a
to
156
d
of low dielectric constant can be prevented. Therefore, reaction between interconnections
145
b
to
145
d
and insulators
156
a
to
156
d
having low dielectric constant can be prevented. Accordingly, degradation of electrical characteristics of the semiconductor device caused by fluctuation of electrical characteristics of interconnections
145
b
to
145
d
can be prevented.
While the semiconductor devices has been miniaturized with the parasitic capacitance of interconnections reduced, cross sectional area of the interconnection itself has been reduced, as the semiconductor devices has been miniaturized. Smaller cross sectional area of the interconnection leads to increased line resistance, which causes degradation of electrical characteristic such as slower speed of operation of the semiconductor device, which is a significant problem. For this reason, use of copper having lower resistance as the material of interconnection in place of conventionally used aluminum, has been studied. When copper is used as the material of the interconnection, line resistance can be decreased even when the interconnection has the same cross sectional area as the aluminum interconnection. Accordingly, higher speed of operation and lower power consumption of the semiconductor device can be attained.
In Damascene process used generally in forming copper interconnection, a silicon nitride film or the like is used as an etching stopper in the process. The silicon nitride film remains in the interlayer insulating film even after the copper interconnection is completed. Here, the silicon nitride film has higher dielectric constant than the silicon oxide film which has been conventionally used as the interlayer insulating film. Therefore, in view of parasitic capacitance of interconnections, sometimes the total capacitance Ctot attains higher than in the conventional example, when copper interconnection is formed. The inventors have found that, as a result, it is difficult to obtain a semiconductor device having superior electrical characteristics and allowing higher speed of operation and lower power consumption simply by replacing the conventional aluminum interconnection with copper interconnection.
When the interconnection is formed using copper, a barrier metal layer is formed on the surface of the interconnection, in order to prevent diffusion of copper to the interlayer insulating film. Here, the barrier metal layer must have a minimum film thickness to maintain its function. Generally, a material for the barrier metal layer has higher electrical resistance than copper. As the semiconductor devices have been miniaturized, the ratio of barrier metal layer with respect to the cross sectional area of the interconnection increases, and therefore influence of the barrier metal layer on the line resistance comes to be non-negligible. Line resistance may be out of the designed range because of variation in film thicknes

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