Oscillators – Ring oscillators
Reexamination Certificate
1999-03-11
2001-03-27
Pascal, Robert (Department: 2817)
Oscillators
Ring oscillators
C327S215000, C327S266000
Reexamination Certificate
active
06208212
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a delay cell used, for example, in a ring oscillator and, more particularly, a delay cell with controlled output amplitude.
BACKGROUND OF THE INVENTION
A ring oscillator can be formed by connecting an odd number of inversions in a ring. This creates an unstable state to produce an oscillation. The oscillation frequency depends on the delay around the ring. The output can be taken at any point in the ring. A ring oscillator made of differential 2N stages, where N is greater than zero, of which only an odd number can invert, has quadrature outputs available. If only single-ended outputs are available, then 4N stages are required. Such ring oscillators are used to generate clocks for digital systems and signals for communication systems. The building block for the ring oscillator is a delay element also known as a delay cell.
In bipolar technology differential amplifiers have been used as the time delay element in the ring oscillator. The differential amplifiers are connected either inverting or non-inverting. The differential amplifier comprises an emitter coupled transistor pair, with the emitters connected to a current source. The bases are connected to a differential input. The collectors are connected via load resistors to a positive voltage source. The differential output is taken across the collectors via buffer transistors. The current source is varied to control the delay. As the current is increased, the speed of the stage increases, resulting in time delay decrease and a ring oscillator frequency increase. However, the output swing is defined by source current multiplied by load resistance. Because load resistance is not variable, the output level decreases with decreases in source current. This reduces the usable frequency range because the output becomes too low to drive the next stage in the ring. The low frequency usable range is also hindered because too high of a signal swing on the internal nodes comprising the collectors of the emitter-coupled pair on the load resistors can cause the transistors of the emitter-coupled pair to leave their intended linear operating region. This makes the stage both slower and its output unsymmetrical, and requires a more complex biasing scheme to control, or even a higher supply voltage.
Another prior design removes output level variance on frequency. A bias current is switched between two paths. The first path is a high speed path and the second path is a lower speed path comprised of two stages. The final output frequency is determined by a current switch which sets the portion of bias current flowing through the high speed paths single stage and the second stage of the slower path. Because the high speed stage and the second stage of the slower path share the load, the output is always determined by the total bias current multiplied by the load resistance. Because both are constant, the output is constant versus frequency. However, this circuit requires an additional bias current through the first stage of the slow path. Also, such delay cell is limited by a two-stage slow path. The minimum difference between the fast and slow path is limited by the maximum speed of the first stage of the slow path.
The present invention is directed to overcoming the problems discussed above in a novel and simple manner.
SUMMARY OF THE INVENTION
Broadly, there is disclosed herein a delay circuit with controlled output amplitude.
The delay circuit comprises a fast delay stage comprising a differential amplifier for connection to a differential input. A slow delay stage comprises a differential amplifier connected in parallel with the fast delay stage differential amplifier and having capacitance means for setting a delay amount. A current source develops a bias current. A current switch is connected between the current source and the fast delay stage and the slow delay stage to switch the bias current between the fast delay stage and the slow delay stage. An output circuit is connected to the fast and slow delay stages for developing a differential output delayed relative to the differential input responsive to a ratio between fast delay stage current and slow delay stage current.
It is a feature of the invention that each of the differential amplifiers comprises an emitter coupled transistor pair with the differential input connected across bases of the transistors of the pair. The output circuit comprises a pair of load resistors connected between a voltage source and the collectors of the transistor pairs. The capacitance means comprises first and second capacitors connected oppositely between collectors of the slow delay stage transistor pair.
It is another feature of the invention that the output circuit comprises a pair of load resistors connected between a voltage source and the parallel connected fast delay stage and slow delay stage. The output circuit further comprises a cascode circuit connected between the slow delay stage and the load resistors to isolate capacitance of the slow delay stage from the fast delay stage. The cascode circuit may also be connected between the fast delay stage and the load resistors. The cascode circuit comprises cascode transistors.
It is a further feature of the invention that the output circuit comprises a buffer circuit including first and second emitter follower transistors.
It is yet another feature of the invention that the current switch comprises an emitter coupled transistor pair having the emitters connected to the current source, collectors connected to the respective fast and slow delay stages, and bases connected to a differential control input.
There is disclosed in accordance with another aspect of the invention a ring oscillator comprising a plurality of delay cells which control output amplitude. Each delay cell comprises a fast delay stage including a differential amplifier for connection to a differential input, and a slow delay stage including a differential amplifier connected in parallel with the fast delay stage differential amplifier and having capacitance means for setting a delay amount. A current source develops a bias current. A current switch is connected between the current source and the fast delay stage and the slow delay stage to switch the bias current between the fast delay stage and the slow delay stage, and an output circuit is connected to the fast and slow delay stages for developing a differential output delay relative to the differential input responsive to a ratio between fast delay stage current and slow delay stage current. Means are provided for connecting the plurality of delay cells to provide a ring, the connecting means connecting differential inputs of each delay cell to the differential output of another delay cell, wherein an odd number of said connections are inverted connections. Control means are connected to the current switch of each delay cell to control cell delay and thus oscillator frequency.
It is a feature of the invention that the oscillator generates quadrature outputs.
In accordance with the invention, the delay cell, when switched for fast operation, uses all of the bias current for the fast stage. Thus, the overall current consumption is lower for the same performance level as with prior delay cells. Also, the delay cell is limited to second-order effects of transistor device speed for higher average bias currents, and the speed of the slow stage can approach the speed of the fast stage.
Further features and advantages of the invention will be readily apparent from the specification and from the drawings.
REFERENCES:
patent: 4833695 (1989-05-01), Greub
patent: 4866314 (1989-09-01), Traa
patent: 5066877 (1991-11-01), Hamano et al.
patent: 5559476 (1996-09-01), Zhang et al.
Ericsson Inc.
Glenn Kimberly E
Pascal Robert
Wood Phillips VanSanten Clark & Mortimer
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