Static information storage and retrieval – Floating gate – Particular biasing
Reissue Patent
1999-12-02
2001-08-07
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185060, C365S185260
Reissue Patent
active
RE037311
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a parallel type nonvolatile semiconductor memory device which is electrically programmable and erasable and a method of using the device, and more particularly to a parallel type nonvolatile semiconductor memory device applied, preferably, to a large scale integration scheme and a method of using the device.
In general, a parallel type nonvolatile semiconductor memory device which is electrically programmable and erasable is constituted, for example, by nonvolatile memory cells comprising a plurality of MOS field effect transistors (hereinafter referred to as “MOS transistors”) each provided with an n-type drain region and an n-type source region formed on a p-type silicon substrate, a gate insulation film formed on a surface of the substrate including these regions, a floating gate formed on the insulation film, and a control gate formed on the floating gate through an interlayer insulation film and, respectively, are arranged in a matrix. The plural nonvolatile memory cells constituting a nonvolatile memory cell array are used in that control gates are connected to each other by individual word lines in each row of nonvolatile memory cell, drain regions are connected to each other by individual data lines in each column of nonvolatile memory cell, and source regions are connected to each other by individual source lines in each column (refer to Japanese Patent Laid-Open No. Hei 6-77437 for example).
Programming and erasing of data are performed by utilizing tunnel phenomena of electrons (Fowler-Nordheim phenomena: hereinafter referred to as “F-N phenomena”) in a gate insulation film. That is, when negative voltage is applied to a control gate, positive voltage is applied to a drain region and a source region is held to the substrate voltage (zero voltage), the F-N phenomena are generated on the gate insulation film in an overlapped portion of the drain region and the floating gate, and electrons are ejected from the floating gate to the drain region and data is programmed.
On the other hand, when positive voltage is applied to the control gate and the drain region and the source region are held to the substrate voltage, the F-N phenomena are generated on the whole surface of the gate insulation film and electrons are injected from the whole of the channel region to the floating gate and data is erased.
In the prior art as above described, in order to write data efficiently, it is preferable that the drain region possesses a withstanding voltage of at least 6V or more. Therefore, it is necessary that an overlapped portion with length of at least 0.15 &mgr;m is formed between the floating gate and the drain region. Since the effective length of the floating gate, which can be formed by the process technology in the prior art, is about 0.4 &mgr;m even in the case of minimum, when the length of the overlapped portion is made about 0.15 &mgr;m, the channel length of about 0.15 &mgr;m can be secured by limiting the length of the overlapped portion of the floating gate and the source region to about 0.1 &mgr;m. Therefore, a method has been adopted in the prior art whereby the drain region is formed larger than the source region asymmetrically thereby the withstanding voltage of the drain region is secured.
However, in the present state that the process technology is developed significantly and the fine pattern processing of the floating gate with the effective length of about 0.25 &mgr;m becomes possible, even if the length of the overlapped portion of the floating gate and the source region and the channel length can be suppressed to about 0.05 &mgr;m and about 0.1 &mgr;m respectively, since the length of the overlapped portion of the floating gate and the drain region can not be made 0.15 &mgr;m or more, when the asymmetric structure as in the prior art is adopted, it is difficult that the high integration memory device of 256 mega bits or more be realized.
Besides this, in the prior art, when data is programmed, since positive voltage is applied to the drain region (data line) and negative voltage is applied to the control gate (word line), it can not be prevented that a leak current flowing through a depletion region (band-to-band tunneling current) is generated under the gate insulation film of the drain region. Positive holes as origin of this leak current are partly captured within the gate insulation film and accelerate the deterioration of the insulation film and cause the programming and erasing cycle to be decreased significantly.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor integrated circuit of novel configuration and its using method, where the above-mentioned problems in the prior art are solved, and a nonvolatile memory device having quite high density and being electrically programmable can be easily realized.
The problems in the present invention, as above described, can be solved in that on a semiconductor substrate of a first conductive type is formed a well layer having the same conductive type as that of the substrate and being electrically separated from the substrate, and a MOS transistor having a drain region and a source region respectively formed within the well layer is used as a memory cell. Well layers of a plurality of memory cells constituting a memory array are connected to each other by a well wiring commonly so that operation voltage different from that of the semiconductor substrate is applied thereto. Control gates are connected to each other, drain regions are connected to each other and source regions are connected to each other by individual word lines, data lines or source lines in each row or column in similar manner to that of the prior art as above described.
In a memory device and a method of use thereof according to the present invention, being different from the above-mentioned prior art in structure, injection of electrons to the floating gate is defined as data programming, and ejection of electrons from the floating gate is defined as data erasing. Erasing of data is performed in that prescribed positive voltage is applied to the well wiring and other prescribed voltage (for example, negative voltage) lower than the positive voltage is applied to a selected word line (a word line leading to a control gate of a memory cell desired to be erased). In this case, the voltage Vf applied to the floating gate of the selected memory cell becomes a value determined by formula (1), and as a result of that the high electric field shown in formula (2) is applied to the whole surface of the gate insulation film, the F-N phenomena are generated to the whole of the insulation film and electrons are ejected from the floating gate, and the threshold voltage of the memory cell can be selected to a lower range of 0.5V-1.5V. In addition, in formula (1) and formula (2), Vp indicates voltage applied to the well layer (subscript p means plus value), Vn indicates voltage of the control gate (subscript n means minus value), Cr indicates coupling ratio (ratio of capacitance of the gate to the whole capacitance viewing from the floating gate), and Tox indicates thickness of the gate insulation film respectively.
Vf=Cr(Vn−Vp)+Vp (1)
−(Vf−Vp)/Tox (2)
The data erasing can be executed regarding all memory cells connected to the selected word line collectively and simultaneously. Therefore, one word line is defined as a sector of 512 bytes for example, thereby the efficient data erasing in individual units of 512 bytes becomes possible. However, since positive voltage is applied to the well layers of the all memory cells through the well wiring, if an unselected word line is left to the open state, in memory cells connected to the word line, as a result of that a weak electric field directed from the floating gate towards the well layer is applied to the gate insulation film, erase-disturb phenomena are generated that electrons go out of the floating gate gradually. The phenomena can be prevented in that the
Adachi Tetsuo
Kato Masataka
Kobayashi Takashi
Kume Hitoshi
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Zarabian A.
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