Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
1999-04-21
2001-07-17
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S017000, C712S015000, C710S120000, C710S120000, C710S061000, C370S406000
Reexamination Certificate
active
06263415
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to multi-processor computer systems and more particularly to high availability crossbar switch architecture.
BACKGROUND ART
High performance, multi-processor systems with a large number of microprocessors are built by interconnecting a number of node structures, each node containing a small number of microprocessors. This necessitates an interconnection network which is efficient in carrying control information and data between the nodes of the multi-processor.
In the past, crossbar switches, which route communications between the “nodes” of a network, included logic for determining a desired destination from message header, and for appropriately routing all of the parallel bits of a transmission; e.g., 64 bits in parallel for a 64 bit microprocessor. A configuration such as this presents inherent scalability problems, principally because its number of nodes or ports limits each crossbar switch. For example, a typical crossbar switch might service four nodes in parallel, and route 64 bits to one of the four nodes; if more nodes were desired, multiple crossbar switches would be cascaded to support the additional nodes. Such a configuration is not readily scalable either in terms of bandwidth; i.e., such a system could not readily be reconfigured to handle 128 bits in parallel to support higher-performance systems, or because the more cascaded structures, the greater the routing overhead and associated latency. Further, it is difficult to achieve high availability or redundancy with such a configuration.
Thus, a method or architecture has been long sought and long eluded those skilled in the art, which would be scalable and re-configurable while having low latency and high redundancy. The system would be packet switched and provide a high availability (HA) crossbar switch architecture.
DISCLOSURE OF THE INVENTION
The present invention provides a new crossbar switch which is implemented by a plurality of parallel chips. Each chip is completely programmable to couple to every node in the system, e.g., from one node to about one thousand nodes (corresponding to present-day technology limits of about one thousand I/O pins) although conventional systems typically support no more than 32 nodes. The first crossbar switch can be implemented to support only one node such that one chip can be used to route all 64 bits in parallel for 64 bit microprocessors or 128 bits in parallel for a 128 bit processor. A second crossbar switch in parallel with the first crossbar switch provides the redundancy in system operation.
The present invention provides a flexible structure that allows dynamic programming of its data routing, such that one commercial crossbar system can support many different network architectures. With dynamic scalability, if nodes are added to an existing system, then different programming may be used to reconfigure the crossbar switches. A parallel setup of such a system can further provide scalable redundancy.
The present invention provides a multi-processor system interconnection network based on a scalable, re-configurable, low latency, packet switched and highly available crossbar switch architecture.
The present invention further provides a scalable system by parallelizing the interconnection network into a number of identical crossbar switches. This enables implementation of the interconnection network function without pushing the limits of integrated circuit and system packaging technologies. At the same time, the invention provides a method to substantially increase the bandwidth of a multi-processor system and redundancy.
The present invention further provides a method to re-configure the ports of the crossbar switches so that a smaller number of crossbar switch circuits can provide the required bandwidth and redundancy when the multi-processor system consists of a small number of node structures, thus reducing system hardware cost.
The invention described also provides for a redundant interconnection network in parallel to the primary interconnection network, thus significantly enhancing the reliability and high-availability of the multi-processor system.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 4379326 (1983-04-01), Anastas et al.
patent: 4965793 (1990-10-01), Polzin et al.
patent: 4968977 (1990-11-01), Chinnaswamy et al.
patent: 5088091 (1992-02-01), Schroder et al.
patent: 5107493 (1992-04-01), Eng et al.
patent: 5179669 (1993-01-01), Peters
patent: 5191578 (1993-03-01), Lee
patent: 5261059 (1993-11-01), Hedberg et al.
patent: 5280474 (1994-01-01), Nickolls et al.
patent: 5339396 (1994-08-01), Muramatsu et al.
patent: 5386511 (1995-01-01), Murata et al.
patent: 5471592 (1995-11-01), Gove et al.
patent: 5513371 (1996-04-01), Cypher et al.
patent: 5522083 (1996-05-01), Gove et al.
patent: 5555543 (1996-09-01), Grohoski et al.
patent: 5598408 (1997-01-01), Nickolls et al.
patent: 5598568 (1997-01-01), Frisch
patent: 0551188A2 (1993-01-01), None
patent: 2262173 (1993-06-01), None
patent: 2262174 (1993-06-01), None
patent: 2262175 (1993-06-01), None
Hewlett-Packard Co
Pan Daniel H.
LandOfFree
Backup redundant routing system crossbar switch architecture... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Backup redundant routing system crossbar switch architecture..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Backup redundant routing system crossbar switch architecture... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2447748