Data processor having 2n bits width data bus for context switchi

Details Data processor having 2n bits width data bus for context switchi Data processor having 2n bits width data bus for context switchi

1990-12-13

1996-01-02

Lee, Thomas C.

Boots, shoes, and leggings

395308, 364DIG2, 36492798, 364DIG1, 3642328, 3642402, G06F 900, G06F 930, G06F 1300, G06F 1340

Patent

active

054817340

ABSTRACT:
A data processor being provided with a data register having a double width of the width of a general purpose register for inputting/outputting data with respect to the operand access unit, and a data transfer path which is composed of a plurality of buses between the register file and the data register and which simultaneously transfers two data, in which, in the case where an LDCTX instruction which is the instruction for loading data to more than two register is executed, a combined data of two data each of which is to be loaded in different register is transferred from the operand access unit to the data register, and high order 4 bytes of data and low order 4 bytes of in the data register are simultaneously transfers to two register through two data transfer paths, respectively, and in the case where an STCTX instruction which is the instruction for storing data from more than two register is executed, contents of the two registers are simultaneously transferred to a high order 4 bytes and a low order 4 bytes of the data register, respectively, and two data are combined into one data in the data register, thereafter the combined data is transferred to the operand access unit in one memory accessing.

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Eggebrecht L, "Interfacing to the IBM Personal Computer", 1990 pp. 59-62, 67-68.

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