Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-03-29
2001-03-20
Powell, William (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C134S001200, C216S018000, C216S067000, C438S743000
Reexamination Certificate
active
06204192
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit structures. More particularly, this invention relates to a process for cleaning etch residues, including copper oxides, from openings formed through one or more layers of low dielectric constant materials formed over copper metallization.
2. Description of the Related Art
In the construction of integrated circuit structures, dielectric materials such as silicon oxide (SiO
2
) have been conventionally used to electrically separate and isolate or insulate conductive elements of the integrated circuit structure from one another. However, as the spacing between such conductive elements in the integrated circuit structure have become smaller and smaller, the capacitance between such conductive elements through the silicon oxide dielectric has become of increasing concern. Such capacitance has a negative influence on the overall performance of the integrated circuit structure in a number of ways, including its effect on speed of the circuitry and cross-coupling (crosstalk) between adjacent conductive elements.
Because of this ever increasing problem of capacitance between adjacent conductive elements separated by silicon oxide insulation, as the scale of integrated circuit structures continues to reduce, the use of other insulation materials having lower dielectric constants than conventional silicon oxide (SiO
2
) has been proposed. One such class of material is an organo silicon oxide material wherein at least a portion of the oxygen atoms bonded to the silicon atoms are replaced by one or more organic groups such as, for example, an alkyl group such as a methyl (CH
3
—) group. Such organo silicon oxide dielectric materials have dielectric constants varying from about 2.4 to about 3.5 and are, therefore, of great interest as low dielectric constant substitutes for the conventional silicon oxide (SiO
2
) insulation material.
While the substitution of one or more organic groups for some of the oxygen atoms bonded to the silicon atoms in a silicon oxide insulation material has a beneficial effect in the lowering of the dielectric constant of the organo silicon oxide material, therefore lowering the capacitance between conductive elements separated by such dielectric material, it has been found that the bond formed between the silicon atoms and the organic radicals is not as stable as the silicon-oxygen bond found in conventional silicon oxide (SiO
2
) materials. In particular, for example, when the surface of such a low dielectric constant organo silicon oxide insulation layer is exposed to oxidizing or “ashing” systems, which are used to remove a photoresist mask from the low dielectric constant organo silicon oxide insulation layer, after formation of openings therein, it has been found that the ashing process results in damage to the bonds (severance) between the organic radicals and the silicon atoms adjacent the surfaces of the low dielectric constant organo silicon oxide insulation layer exposed to such an ashing treatment. This severance of the organo-silicon bonds, in turn, results in removal of such organic materials formerly bonded to the silicon atoms along with the organic photoresist materials being removed from the integrated circuit structure. The silicon atoms from which the organic radicals have been severed, and which are left in the damaged surface of the low dielectric constant organo silicon oxide insulation layer, have dangling bonds which are very reactive and become water absorption sites if and when the damaged surface is exposed to moisture.
In copending U.S. patent application Ser. No. 09/281,514, entitled “PROCESS FOR TREATING DAMAGED SURFACES OF LOW DIELECTRIC CONSTANT ORGANO SILICON OXIDE INSULATION MATERIAL TO INHIBIT MOISTURE ABSORPTION”, which was filed by two of us with another Mar. 29, 1999, and is assigned to the assignee of this application, it is proposed to treat such damaged sidewalls with either a hydrogen plasma or a nitrogen plasma. Such a treatment with a hydrogen or nitrogen plasma causes the hydrogen or nitrogen to bond to silicon atoms with dangling bonds left in the damaged surface of the low dielectric constant organo silicon oxide insulation layer to replace organo material severed from such silicon atoms at the damaged surface. Absorption of moisture in the damaged surface of the low dielectric constant organo silicon oxide insulation layer, by bonding of such silicon with moisture, is thereby inhibited.
However, this problem of potential damage to the low dielectric constant organo silicon oxide insulation layer is exacerbated when copper is present as the metal interconnect below the via or opening because the etchants used to form the openings, and/or the chemical cleaning treatments used to either clean away the etch residues or remove the resist mask may also react with any exposed copper surfaces to form copper oxides which must be removed from the opening (via) prior to filling the opening with electrically conductive materials. Copper is sometimes used as the metal interconnect material (and is therefore present at the bottom of the via) because it is a superior electrical conductor to other metals such as aluminum, tungsten, or titanium commonly used as interconnect material in integrated circuit structures. Furthermore, the same desire for faster circuitry which results in the use of low dielectric constant insulation material (to mitigate speed-reducing capacitance) also gives rise to the use of copper as the interconnect metal so the presence of both copper and low dielectric constant insulation material in the same integrated circuit structures must be reckoned with.
In the past, argon plasmas have been used to remove etch residues in openings formed in conventional insulation materials such as silicon oxide (SiO
2
) over non-copper metal interconnects. However, the use of argon as a cleaning gas may also result in undesirable sputtering of the underlying copper metal exposed by the opening. This, in turn, may result in the deposition of such sputtered copper on the low k insulation sidewalls of the via. Since copper is known to migrate into the insulation material (unlike other metals), such deposition of copper onto the sidewalls of the via must be avoided. It was recently proposed by one of us in Zhao et al. U.S. Pat. No. 5,660,682, assigned to the assignee of this invention, to use a mixture of hydrogen and argon gases for removing etch residues in place of the conventional argon plasma, but the potential for sputtering of copper by the argon in the argon hydrogen mixture still remains.
It would, therefore, be desirable to provide a process for cleaning openings such as vias, trenches, etc., formed in low dielectric constant insulation material to remove etch residues, as well as to remove copper oxide residues in such openings, without sputtering copper onto the exposed surfaces of the low dielectric constant insulation material.
SUMMARY OF THE INVENTION
In accordance with the invention, a process is provided for removing etch residues from one or more openings formed in one or more layers of a low dielectric constant insulation material over a copper metal interconnect layer of an integrated circuit structure which includes cleaning exposed portions of the surface of the copper interconnect layer at the bottom of the one or more openings, the process comprising providing an anisotropic hydrogen plasma to cause a chemical reaction between ions in the plasma and the etch residues in the bottom of the one or more openings, including copper oxide on the exposed copper surface, to thereby clean the exposed portions of the copper surface, and to remove the etch residues without sputtering the copper at the bottom of the opening.
REFERENCES:
patent: 3012861 (1961-12-01), Ling
patent: 3178392 (1965-04-01), Kriner
patent: 3832202 (1974-08-01), Ritchie
patent: 3920865 (1975-11-01), Läufer et al.
patent: 4705725 (1987-11-01), Glajch et al.
patent: 4771328 (1988-09-01), Malaviya et al.
patent: 5194333 (1993-03-01), Ohnaka
Catabay Wilbur G.
Hsia Wei-Jen
Zhao Joe W.
LSI Logic Corporation
Powell William
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