Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-01-14
2001-01-23
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S424000, C438S296000, C438S221000
Reexamination Certificate
active
06177333
ABSTRACT:
BACKGROUND
The present invention relates generally to semiconductor devices and, more particularly, to trench isolation process technology for use in memory, image, logic and other semiconductor devices.
Implementing electronic circuits involves connecting isolated devices or circuit components through specific electronic paths. In silicon integrated circuit (IC) fabrication, it is necessary to isolate devices that are formed in a single substrate from one another. The individual devices or circuit components subsequently are interconnected to create a specific circuit configuration.
As the density of the devices continues to rise, parasitic inter-device currents become more problematic. Isolation technology, therefore, has become a critical aspect of integrated circuit fabrication.
For example, dynamic random access memory (DRAM) devices generally comprise an array of memory cells for storing data and peripheral circuits for controlling data in the memory cells. Each memory cell in a DRAM stores one bit of data and consists of one transistor and one capacitor. Within the array, each memory cell must be electrically isolated from adjacent memory cells. The degree to which large numbers of memory cells can be integrated into a single IC chip depends, among other things, on the degree of isolation between the memory cells.
Similarly, in metal-oxide-semiconductor (MOS) technology, isolation must be provided between adjacent devices, such as NMOS or PMOS transistors or CMOS circuits, to prevent parasitic channel formation. CMOS circuits can be used, for example, to form the pixels in a photosensitive imaging device and must be isolated from one another. In the case of CCD or CMOS imagers which are intentionally fabricated to be sensitive to light, it is advantageous to provide both electrical and optical isolation between pixels.
Shallow trench isolation (STI) is one technique which can be used to isolate devices such as memory cells or pixels from one another. In general, a trench is etched into the substrate to provide a physical barrier between adjacent devices. Refilled trench structures, for example, consist essentially of a sub-micron recess formed in the silicon substrate by a dry anisotropic or other etching process. The recess is filled with a dielectric such as a chemical vapor deposited (CVD) silicon dioxide (SiO
2
). The filled trench then is planarized by an etchback process so that the dielectric remains only in the trench and its top surface level with that of the silicon substrate.
Refilled trench isolation is sometimes categorized according to the dimensions of the trench: shallow trenches (less than about 1 micron), moderate depth trenches (1-3 microns), and deep narrow trenches (greater than 3 microns deep, less than 2 microns wide). Shallow trench isolation is used, for example, to isolate devices.
To enhance the isolation further, ions can be implanted in the silicon substrate in the area directly beneath the trench. However, as noted, for example, in S. Nag et al., “Comparative Evaluation of Gap-Fill Dielectrics in Shallow Trench Isolation for Sub-0.25 &mgr;m Technologies,” IEEE IEDM, pp. 841-844 (1996), some ion implants can result in high current leakage. In particular, when ions are implanted in the substrate close to the edges of the trench, current leakage can occur at the junction between the active device regions and the trench. Similarly, if the trench is shallow, then a photon impinging on a particular pixel of a photosensitive device may diffuse under the trench isolation structure to an adjacent pixel, resulting in detection of the photon by the wrong pixel. Accordingly, it is desirable to improve the trench isolation techniques to address those and similar problems.
SUMMARY
In general, according to one aspect, a method of fabricating an integrated circuit includes forming an isolation trench having a bottom and sidewalls in a semiconductor substrate and partially filling the trench with a dielectric material so that at least the sidewalls of the trench are coated with the dielectric material. Ions are implanted into the substrate in regions directly below the isolation trench after partially filling the trench with the dielectric material.
The dielectric along the sidewalls of the trenches can serve as a mask so that substantially all of the ions implanted below the isolation trenches are displaced from the active regions. After the ions are implanted in the substrate below the trenches, the remainder of the trench can be filled with the same or another dielectric material.
Various implementations include one or more of the following features. In general, the energy of the ions and the thickness of the dielectric layer can be selected so that the dielectric layer along the sidewalls of the trench serves as a mask that prevents ions from becoming implanted in the substrate in a vicinity near edges of the trenches. Depending on the particular application, shallow and/or deep ion profiles can be implanted into the substrate.
Partially filling the trench with a dielectric material can include growing an oxide layer such as silicon dioxide or depositing an insulating material using chemical vapor deposition or a combination of thermal growth and chemical vapor deposition. Preferably, the dielectric layer has a sidewall thickness less than about forty percent the width of the trench.
The trench isolation technique can be used to fabricate a variety of integrated circuits which can include devices that exhibit reduced current leakage and/or reduced optical cross-talk. Integrated circuits including imaging devices, such as CMOS imagers and CCD imagers, memory devices, such as DRAMs, and logic devices are representative of devices that can be formed according to the invention. More generally, the techniques described by this invention can be used to provide isolation for an active region on any semiconductor device. Impurity-doped regions can be formed in the active regions and may include, for example, storage nodes for a memory device, photosensitive elements for an imaging device, or active elements for a logic device, as well as others active semiconductor elements.
In some implementations, shallow ion implants are provided to establish field threshold voltage implants to improve the electrical isolation between active areas. Deep implants can be provided, for example, to reduce the optical cross-talk between adjacent photosensitive pixels in CMOS or CCD imagers.
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Blum David S
Bowers Charles
Dickstein , Shapiro, Morin & Oshinsky, LLP
Micro)n Technology, Inc.
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