Pulse or digital communications – Synchronizers
Reexamination Certificate
1997-06-03
2001-03-27
Bocure, Tesfaldet (Department: 2731)
Pulse or digital communications
Synchronizers
Reexamination Certificate
active
06208701
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
SYNCHRONIZATION EQUIPMENT
The present invention relates to a synchronizing apparatus for use in the receiver of a digital communication system.
2. Description of the Related Art
Digitalization in communication has remarkably advanced lately and is still progressing. In digital communication, the receiving side needs means for pulling frame synchronization in with high speed and high precision.
A conventional synchronizing apparatus for pulling-in of synchronization employs a PLL (phase-locked loop) as described in “HOW TO USE PLL-IC” (written by Tuneyasu Hata and Kazuaki Furukawa, and published by Akiba, pp. 20-32, November 1976). With reference to
FIG. 1
, this apparatus has a digital VCO (voltage-controlled oscillator) 1 for finally producing a signal synchronized with an input signal under the control of the PLL, a binary quantizing phase comparator 2 for comparing the phase of the input signal with the phase of the output signal from the digital VCO
1
, and producing data of +1 or −1 as a result of the comparison, and a sequential loop filter
3
for counting the output signal from the binary quantizing phase comparator
2
and supplying a correction signal to the digital voltage-controlled oscillator
1
when the count exceeds a certain value (N). The binary quantizing phase comparator
2
includes a phase comparator
4
for comparing the phase of the input signal with the phase of the output signal from the digital VCO
1
, and a quantizer
5
for quantizing the result from the comparator into a binary value. The digital VCO
1
includes a fixed oscillator
6
for oscillating at a fixed frequency, a pulse addition/removal circuit
7
for adding or removing a pulse to or from the output of the fixed oscillator
6
when the sequential loop filter
3
generates the output signal, and a frequency divider
8
for dividing the frequency of the output signal from the fixed oscillator
6
to or from which the pulse has been added or removed.
In this synchronizing apparatus, the phase comparator
4
of the binary quantizing phase comparator
2
compares the phase of the input signal with the phase of the output signal from the digital VCO
1
. The quantizer
5
produces a value of −1 when the phase of the output signal from the digital VCO
1
is larger than that of the input signal, or when the output signal is ahead of the input signal, but it produces a value of +1 when it is smaller than that, or when the output signal is behind the input signal. The sequential loop filter
3
counts the output from the quantizer
5
, and supplies to the pulse addition/removal circuit
7
the correction signal for controlling a pulse to be removed when the count arrives at +N, or for controlling a pulse to be added when the count reaches −N.
Therefore, in this synchronizing apparatus used as a frame synchronizer, when the phase of the output signal from the digital VCO
1
shifts in the positive or negative direction relative to the phase of the frame synchronizing signal, the sequential loop filter
3
supplies the first correction signal N frames after the start of pulling-in of synchronization.
When the correction signal is supplied to the digital VCO
1
, the pulse addition/removal circuit
7
inserts a pulse in the output signal from the fixed oscillator
6
or removes it therefrom in response to this correction signal. Since the oscillation frequency of the fixed oscillator
6
is selected to be R times as high as the input frequency in order that the quantized value for phase control can be reduced, the output signal from the fixed oscillator
6
in which a pulse has been inserted or from which a pulse has been removed by the pulse addition/removal circuit
7
is supplied to the frequency divider
8
where its frequency is divided by R, and the frequency-divided signal is produced from the output end of the digital VCO
1
.
When there is still a phase difference between the output signal from the digital VCO
1
and the input signal even after the insertion or removal of a pulse, the above operations are repeated, and finally the output signal from the digital VCO
1
is controlled so that the phase difference between the output signal from the digital VCO
1
and the input signal can be minimized.
In this apparatus, if &phgr; is the initial phase difference at the time of pulling-in of frame synchronization, the time in which the phase pulling-in is caused within an error &dgr; is given by the following equation (1).
T
0
={(&phgr;−&dgr;)
R/
360
}×N
(1)
where 360°/R is the phase change in one cycle.
The average time in which the frame synchronization is established is derived from Eq. (1) as in the following equation (2).
T
AVE
=
∫
0
180
{
(
φ
-
δ
)
360
/
R
×
N
}
ⅆ
φ
=
(
0.25
-
δ
/
360
)
N
R
(
2
)
Here, if it is assumed that &dgr;=180/R, the frequency for comparison is 50 Hz, or the frame frequency of full rate of PDC, and the oscillation frequency of the fixed oscillator
6
is 12.6 kHz, then R=252 can be obtained, and thus the average pull-in time is 62.5×N, or 3.125 seconds.
However, since the above conventional synchronizing apparatus employs an analog PLL, it is easily affected by temperature change, timing aging and environmental variation such as voltage fluctuation. In addition, after synchronization is locked by an alternating pattern for synchronization, synchronization holding by use of information symbol is made unstable by the information symbol pattern.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a high-performance synchronizing apparatus all formed of digital circuits to have high resistance to environmental change irrespective of whether the transmitted symbol pattern is an alternating pattern for synchronization or information symbol that has no random property.
According to the invention, there is provided a synchronizing apparatus that is all formed of digital circuits, detects the zero-cross points of a received signal of IF band at N times as high as the symbol rate, and establishes the optimum symbol synchronization from the histogram to the detected time. Therefore, in the present invention, since the histogram of the zero-cross points is detected, erroneous operation is not caused even when zero-cross points do not successively occur during some symbol periods in any symbols like information symbol. In addition, when the burst length is short or when the clock precision is very high, synchronization can be established and held by a small number of symbols, and thus low power consumption can be achieved by stopping the synchronizing circuit. Moreover, even when the burst length is long or when the clock precision is low, synchronization can be detected in information symbols, and thus synchronization tracking can be realized by the addition of simple circuits.
The first synchronizing apparatus according to the present invention includes means for detecting a code from an input signal, means for detecting from the code the variable points of the code at several times as high as the symbol rate, means for calculating a histogram of the detected variable points of the code to time, and means for deciding that the phase number at which the calculated histogram takes the maximum value is a symbol synchronization point. In other words, the zero-cross points of a signal of IF band are detected at N times the symbol rate, a histogram to the detected time (0 to N−1) is calculated, and the time (0 to N−1) at which the histogram takes the maximum value within a certain detected period is selected as a symbol clock, thereby establishing symbol synchronization.
The second synchronizing apparatus according to the present invention includes means for detecting a code from an input signal, latch means for detecting from the code the variable points of the code at several times as high as the symbol rate,
Hiramatsu Katsuhiko
Sudo Hiroaki
Uesugi Mitsuru
Bocure Tesfaldet
Frank Robert J.
Matsushita Electrical Industrial Co. Ltd.
Venable
Wood Allen
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