High speed clock having a programmable run length

Details High speed clock having a programmable run length High speed clock having a programmable run length

1999-11-04

2001-05-01

Wambach, Margaret R. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Sequential readout of plural counters or sequential sampling...

C377S027000, C377S033000

Reexamination Certificate

active

06226345

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a system and method embodied in a high speed programmable counter that will run for a specified number of cycles, and in particular to a high speed programmable counter for large numbers of cycles using cascaded counters with a programmable branch that together provide the capability to generate a desired number of clock pulses within an extremely wide range.
2. Description of the Related Art
Microprocessors commonly use counters to provide clock signals to drive a variety of logic circuits within the microprocessor. As the complexity of microprocessors and logic elements increases, the need for larger counters, or counters that can count to greater numbers, into the millions or higher, also increases. However, as the size of a counter increases, the numbers of levels of logic required to drive the counter also increases. Consequently, the speed of that counter effectively decreases as the complexity of the logic increases. In other words, as the counters ability to count to higher numbers increases, a proportional decrease in the speed of that counter is experienced. Consequently, such counters are often too slow to drive the logic elements of microprocessors at the necessary speeds as the speeds of the microprocessors increase.
In order to address the issue of decreased speed in large counters, smaller counters have been cascaded together. In effect, cascading of two or more relatively small counters allows much higher clock speeds to be achieved by the cascaded counters than can be achieved by simply using a single large counter. However, unlike a single large counter, simply cascading two or more smaller counters does not provide the capability to generate a specific number of clock pulses that is not a modulus of the bit size of the individual counters within the cascade. As a result, when such counters are used, they will typically be set to count beyond the required number of clock pulses, thereby resulting in wasted clock pulses and decreased system performance.
Further, microprocessors often contain a large number of individual logic circuits that may each require a different, yet specific, number of clock pulses to perform a certain function. As a result, different counters are often used to provide different numbers of clock pulses to specific logic circuits. Consequently, the ability to achieve multiple specific count numbers, such as for example a prime number count, is not possible with a simple cascade of counters. Therefore, what is needed is a system and method for using a variable or programmable counter to generate specific numbers of clock pulses at high speed.
SUMMARY OF THE INVENTION
To overcome the limitations in the related art described above, and to overcome other limitations that will become apparent upon reading and understanding the present application, the present invention is embodied in a programmable counter that uses cascaded sub-counters with a programmable branch to provide the capability to generate a desired number of clock pulses at high speed.
The system and method of the present invention achieves precise control over the number of clock pulses generated by a programmable counter. In general, a programmable initialization counter is coupled to an initialization clock generator to generate a programmable number of clock pulses. Further, one or more event clock generators are disposed in series between primary and secondary programmable cascaded counters that are coupled to the initialization clock.
Specifically, once the initialization clock generator has completed generation of the specified number of clock pulses, the event clock generators disposed in series between primary and secondary cascaded counters, each generate, in series, a clock for each count of the secondary cascaded counter. However, each of the event clock generators is also capable of being enabled or disabled via an enable latch so that they will generate clock pulses when enabled. Once the secondary cascaded counter has completed counting to a specified number, the count of the primary cascaded counter is decremented. Next, a programmable branch pointer coupled to the primary cascaded counter branches back to either the programmable initialization counter, the secondary cascaded counter, or to any of the one or more event clock generators disposed in series between primary and secondary cascaded counters. This process preferably repeats until the count of the primary cascaded counter has reached the specified number, at which point the programmable counter of the present invention preferably stops.
The programmable branch pointer preferably branches back to one or more specific branch points so that, in combination with the initial values programmed into the initialization counter as well as the primary and secondary cascaded counters, the total clock count of the programmable counter of the present invention can be defined exactly.
The programmable counter of the present invention can achieve an extremely wide range of counts. The programmable counter allows for a reduction in the number of unique counters in a system, with a corresponding reduction in system cost. Further, because the bit depth of the cascaded counters can be relatively shallow, the speed of a programmable counter in accordance with the present invention is fast enough to meet the clock demands of extremely fast microprocessors.
For illustrative purposes only, one example of a programmable counter according to the present invention uses a four-bit initialization counter followed by a clock generator and both primary and secondary cascaded counters that are also four-bits wide, an event clock generator disposed between the primary and secondary cascaded counters, and a programmable branch pointer coupled to the primary cascaded counter. With a four-bit depth, the initialization counter can be programmed to count to any number between 0 and 15. Therefore, because the initialization clock may be enabled or disabled via an enable latch, the initialization clock generator can generate from 0 to 16 clock pulses. Further, the four-bit cascaded counters with the event clock generator are capable of generating any number of counts between 0 and 255, and thus from 0 to 256 clock pulses. Consequently, the programmable counter of this trivial example is capable of reaching any specific count, and thus clock pulses, between 0 and 272. Further, a maximum count of 512 is also possible given this configuration.
The programmable counter of the present invention is not limited to the case illustrated above, either in the bit depth of the initialization counter, the bit depth of the primary or secondary cascaded counters, or in the number of event clock generators disposed between the primary and secondary cascaded counters. Further, while the bit depth of the initialization counter, and the primary and secondary cascaded counters were equal in the example, the programmable counter of the present invention may use different bit depths for each of the components of the programmable counter.
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings wherein like reference numbers represent like parts of the invention.


REFERENCES:
patent: 4398085 (1983-08-01), Benedict

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