Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Statutory Invention Registration
1997-06-25
2001-09-04
Pihulic, Daniel T. (Department: 3662)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Statutory Invention Registration
active
H0001993
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to processors and, more particularly, to circuitry for performing floating-point division and squareroot operations.
BACKGROUND
Many currently available processors are configured to perform floating-point arithmetic such as, for example, division and squareroot, in compliance with the IEEE Standard for Binary Floating-Point Arithmetic (ANSI/IEEE Std 754-1985). which is incorporated herein by reference. In these processors, the exponent of the result of the operation is generally calculated after the mantissa computation is completed. Thus, the calculation of the resulting exponent is in the critical path of the division and squareroot operations.
Moreover, the mantissa computation can require twenty or more processor clock cycles to complete when using double precision. Thus, calculation of the resultant exponent has a relatively long latency. As is well known, the resultant exponent can then be checked for overflow and underflow exceptions, which are defined in the aforementioned IEEE standard.
The relatively long latency of the resulting exponent calculation can become problematic in the so-called superscalar type of processor. In particular, because superscalar processors may concurrently execute two or more instructions, an instruction may complete after a later-occurring instruction, which can result in an error. For example, an error may occur if the later-occurring instruction overwrites a register before a prior floating-point division instruction completes and an overflow or underflow exception occurs for a prior floating-point division operation. The error occurs because when an exception occurs during an instruction (i.e., the trapping instruction), the processor is required to abort all subsequent instructions and request a trap. After the trap-handler completes execution of the trapping instruction, the processor is restarted at the instruction immediately after the trapping instruction. Of course, the completion of a subsequent instruction that overwrites a register before the exception is handled by the trap-handler can cause an error in the program execution.
Because the resultant exponent is not calculated until late in the instruction execution, a conventional solution to this problem is to make a prediction (before the next subsequent instruction completes) of whether an overflow or underflow exception will occur. In this conventional scheme, a pessimistic prediction is performed to ensure that no overflow or underflow exceptions will be missed by the trap-handler. Of course, pessimistic prediction will result in unnecessary traps, which decreases the performance of the processor. Thus, there is a need for a processor capable of early and exact calculation of the resultant exponent, which both increases performance and allows exact prediction of overflow and underflow.
SUMMARY
In accordance with the present invention, a floating-point division circuit is provided that calculates the exact biased resultant exponent before calculating the resultant mantissa. In one embodiment, the circuit includes a carry-save adder, a conditional-sum adder, a multiplexer and a comparator. The conventional carry-save adder is coupled to receive the biased exponent of the dividend (e1), the one's complement of the biased exponent of the divisor (~e2), and the bias (as defined in the aforementioned the ANSI/IEEE Standard for the precision format being used). The ANSI/IEEE Standard specifies that the mantissas of the dividend and operand can be in normalized form.
The conditional-sum adder is coupled to receive the sum and carry resultants of the carry-save adder and operates to output the sums {er0=e1+(~e2)+bias} and {er1=e1+(~e2)+bias+1}. The sum er0 is the resultant biased exponent of the division operation when the resultant mantissa is in a normalized form after calculation. Similarly, the sum er1 is the resultant biased exponent of the division operation when the resultant mantissa is not in a normalized form. The comparator provides an output signal that controls the multiplexer to select the sum er1 when the fraction of the dividend is greater than or equal to the fraction of the normalized divisor. Conversely, when the fraction of the normalized dividend is less than the fraction of the normalized divisor, the comparator causes the multiplexer to select the sum er0. Because the operation of the carry-save adder, conditional-sum adder and the comparator is relatively fast, the exact resultant exponent is available for underflow and overflow detection before the next instruction completes, thereby eliminating the need for pessimistic prediction.
In another embodiment of the invention adapted for determining the resultant exponent of a floating-point squareroot operation, the circuit includes a conditional-sum adder, a multiplexer and a selection logic circuit. The conditional-sum adder is coupled to receive the biased exponent (e2) of the squareroot operand, divided by two (i.e., right-shifted by one bit) and an adjusted bias. The adjusted bias is the exponent bias divided by two, which is incremented if the exponent e2 is odd (i.e., having a least significant bit equal to one). Thus, the conditional-sum adder outputs the sum {er0=½e2+adjusted bias} and the sum {er1=½e2+adjusted bias+1}. The resultant mantissa will end up in normalized form after calculation, except in the case in which all three of the following conditions exist: (i) the fraction of the operand has no zeros; (ii) the e2 is even; and (iii) the rounding mode is rounding to positive infinity (as defined in the aforementioned IEEE standard). The selection logic monitors these three conditions and causes the multiplexer to select er0 to output as the biased resultant exponent in all cases except when all three of the above-conditions occur. When all three of these conditions occur, the selection logic causes the multiplexer to select er1 to output as the biased resultant exponent. This embodiment determines the exact biased resultant exponent before the mantissa calculation is completed. Thus, unlike conventional squareroot circuits, the resultant exponent calculation is taken out of the critical path, thereby improving performance.
In yet another embodiment, the circuit is adapted to calculate the biased resultant exponent of floating-point division, squareroot and multiplication operations. This embodiment includes a bias selection circuit, a first multiplexer, a second multiplexer, a carry-save adder, a conditional-sum adder, a selection logic circuit and an output multiplexer. The first multiplexer selects either e1 for multiplication and division operations or zero for squareroot operations. The second multiplexer selects e2 for multiplication operations, (~e2) for division operations or ½e2 for squareroot operations. The bias selection circuit selects the appropriate bias for the precision format (e.g., single or double precision) for division operations or the adjusted bias (for single or double precision) for squareroot operations. The carry-save adder receives the selected output signals of the first and second multiplexers and the bias selection circuit. The conditional-sum adder receives the carry and sum output signals of the carry-save adder and outputs the sums er0 and er1. The selection logic circuit then causes the output multiplexer to select either er0 or er1 as described above for the floating-point division and squareroot embodiments. For floating-point multiplication operations, the selection logic circuit detects whether the mantissa multiplication resultant is normalized or not normalized. If the mantissa is normalized, the selection logic circuit causes the output multiplexer to select er0 and, conversely, if the mantissa is not normalized, the selection logic circuit causes the output multiplexer to select er1.
In a further refinement of this embodiment, two conventional overflow and two underfiow det
Gunnison Forrest E.
Pihulic Daniel T.
Sun Microsystems Inc.
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