Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2000-03-21
2001-08-07
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S057000
Reexamination Certificate
active
06271687
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit having a differential amplifier which amplifies a small signal, and particularly to a circuit arrangement of a sense amplifier used suitably in a static RAM (Random Access Memory).
There has been known this kind of sense amplifier having a circuit arrangement on a semiconductor chip as shown in FIG.
3
. In the figure, reference symbols CDB
02
, CDT
02
, SAEQB
02
and SACM
02
denote external input signals supplied to the sense amplifier, STB
02
and STT
02
are nodes for output signal lead-out, VCC is a supply voltage, and GND is a ground voltage.
Among the input signals, the CDB
02
is fed to the gate of an NMOS transistor MN
203
, the CDT
02
is fed to the gate of an NMOS transistor MN
204
, the SAEQB
02
is fed to the gates of PMOS transistors MP
201
, MP
202
, MP
203
, MP
206
, MP
207
and MP
208
, and the SACM
02
is fed to the gate of an NMOS transistor MN
205
. The supply voltage VCC is fed to the sources of the PMOS transistors MP
201
, MP
202
, MP
204
, MP
205
, MP
206
and MP
207
. The node STT
02
is connected to the node of drains (joint drains) of the PMOS transistor MP
205
and NMOS transistor MN
202
, the joint gates of the PMOS transistor MP
204
and NMOS transistor MN
201
, and the drain of the PMOS transistor MP
201
.
The PMOS transistor MP
203
has its drain-source path connected between the gates of the PMOS transistors MP
204
and MP
205
. The node STB
02
is connected to the joint drains of the PMOS transistor MP
204
and NMOS transistor MN
201
, the joint gates of the PMOS transistor MP
205
and NMOS transistor MN
202
, and the drain of the PMOS transistor MP
202
. The PMOS transistors MP
206
and MP
207
have their drains connected to the drains of the transistors MN
203
and MN
204
, respectively.
The PMOS transistor MP
208
has its drain-source path connected between the drains of the NMOS transistors MN
203
and MN
204
. The NMOS transistors MN
203
and MN
204
, with their sources connected together, have their drains connected to the sources of the NMOS transistors MN
201
and MN
202
, respectively. The NMOS transistor MN
205
has its source grounded, its drain connected to the joint sources of the NMOS transistors MN
203
and MN
204
, and its gate supplied with the signal SACM
02
.
In this conventional sense amplifier, the NMOS transistor MN
205
serves as a current source, and a pair of NMOS transistors MN
203
and MN
204
connected to the current source form a differential circuit. The PMOS transistor MP
204
and NMOS transistor MN
201
form one inverter and the PMOS transistor MP
205
and NMOS transistor MN
202
form another inverter, with these inverters forming a latch circuit. Accordingly, this sense amplifier is a 3-stage serial connection of the latch circuit, differential circuit and current source.
Normally, the input signal SAEQB
02
is “low”, causing the PMOS transistors MP
203
and MP
208
to equalize and reset the nodes STB
02
and STT
02
to the supply voltage VCC, and the activation signal SACM
02
is “low” so that the sense amplifier stays inactive.
FIG. 4
shows the operating waveforms of this conventional sense amplifier. At a time when a small voltage difference arises between the input signals CDT
02
and CDB
02
, e.g., the CDT
02
voltage is VCC and the CDB
02
voltage is VCC-V
1
(V
1
<VCC), the signal SAEQB
02
is brought to “high” and subsequently the signal SACM
02
is brought to “high”. Consequently, a current I
1
flows through the NMOS transistor MN
204
and a current I
1
-I
2
(I
1
>I
2
) flows through the NMOS transistor MN
203
.
Since the nodes STB
02
and STT
02
are reset to the voltage VCC, the currents I
1
and I
1
-I
2
flow through the NMOS transistors MN
202
and MN
201
, respectively, resulting in a slight voltage difference emerging between the nodes STB
02
and STT
02
(STB
02
voltage becomes lower than STT
02
voltage). This voltage difference is amplified by the latch circuit formed of the PMOS transistors MP
204
and MP
205
and NMOS transistors MN
201
and MN
202
, resulting in an amplified voltage difference produced between the nodes STB
02
and STT
02
.
At the time of arise of a small voltage difference between the input signals CDT
02
and CBD
02
, the signal SACM
02
is brought to “high”, as mentioned above, thereby to activate the sense amplifier, and the reset signal SAEQB
02
is brought to “high”. Consequently, currents flow through the NMOS transistors MN
203
and MN
204
having the input signals CDT
02
and CDB
02
. The values of these currents depend on the difference of gate voltages of the transistors MN
203
and MN
204
. The current difference causes the latch circuit to produce output signals, which are amplified voltages of the input signals CDT
02
and CBD
02
, on the nodes STB
02
and STT
02
.
A sense amplifier having the foregoing arrangement is described in publication: 1992 Symposium on VLSI Circuits Digest of Technical Papers, pp.28-29, for example.
U.S. Pat. No. 4,504,748 discloses in its
FIG. 6
another sense amplifier.
Japanese patent publication JP-A-Hei-5-298887 shows in its
FIG. 12
a sense amplifier, which operates such that the amplifier is rid of equalization in response to the output of data from the DRAM memory cell, and the data is introduced through joint-source PMOS transistors P
1
and P
2
located at the front of the latch circuit.
In regard to the conventional sense amplifier shown in
FIG. 3
, in which the differential circuit and latch circuit are connected in series, the current on the node STB
02
(or STT
02
) is drawn by way of the NMOS transistors MN
201
and MN
203
(or MN
202
and MN
204
), i.e., three series NMOS transistors inclusive of the current source transistor MN
205
, and the high-resistance current path results in an extended output response time on the node STB
02
(or STT
02
). Specifically, as an example of application of this sense amplifier, a cache memory formed of a static RAM operating at a read cycle of 66 MHz takes an output response time of about 2.0 ns. In order to accomplish a cache memory which operates as fast as 100 MHz or higher, a sense amplifier having an output delay time of 1.5 ns or less is required.
The sense amplifier described in the U.S. Pat. No. 4,504,748 does not use a latch circuit formed by CMOS inverters, and therefore a small output voltage amplitude results in a slower signal propagation to the next stage.
In regard to the sense amplifier described in the JP-A-Hei-5-298887, the joint-source PMOS transistors P
1
and P
2
forming the input section of the sense amplifier do not have a common current source, and thus the input section does not have a differential input configuration. On this account, the sense amplifier suffers a smaller operational margin in terms of the input voltage amplitude and a limited amplification, and therefore it cannot deliver an amplified signal of data from a memory cell at a high speed.
A large number of sense amplifiers are used in a memory, and they take up a large proportion of the chip area (e.g., 5% area for a 1M-bit cache memory), and therefore besides the achievement of speed-up without increased power consumption, the reduction of the number of transistors used to form a sense amplifier thereby to reduce the chip area is also desired.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a semiconductor integrated circuit for a sense amplifier capable of reducing the output delay time which is the time length after the sense amplifier is activated and the reset signal (SAEQB
02
) is removed until the amplifier output responses.
Another object of the present invention is to provide a semiconductor integrated circuit for a sense amplifier capable of reducing the output delay time without imposing an increased power consumption, and reducing the number of constituent elements thereby to reduce the chip area.
In order to achieve the above objects, the present invention resides in a semiconductor integrated circuit comprising a differential ampli
Fukui Kenichi
Harada Masashige
Hiraishi Atsushi
Kawachino Haruko
Komiyaji Kunihiro
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Tran Toan
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