Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Reexamination Certificate
1998-07-10
2001-07-03
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
C257S532000, C257S535000
Reexamination Certificate
active
06255675
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to capacitive devices, and more particularly, to a programmable capacitor in an integrated circuit.
BACKGROUND OF THE INVENTION
In integrated circuits (IC's), capacitors are commonly used for data storage, signal filtering, and timing adjustments. However, conventional IC capacitors are difficult and/or costly to produce within an IC due to the nature of current wafer processing techniques.
FIG. 1A
shows a conventional planar capacitor
101
, which comprises a polysilicon layer
130
and an oxide layer
140
formed on a p-type substrate
110
. Polysilicon layer
130
and a depletion region
112
in substrate
110
provide an upper plate and a lower plate, respectively, for planar capacitor
101
. The dielectric constant of oxide layer
140
, along with the area of polysilicon layer
130
and the area of depletion region
112
control the capacitance of capacitor
101
. The simple geometry of planar capacitor
101
is relatively straightforward to manufacture. However, the planar construction of planar capacitor
101
requires that polysilicon layer
130
occupy a large area on the surface of an IC die. This large area makes the construction of planar capacitor
101
increasingly problematic as IC die sizes decrease and device densities increase.
FIG. 1B
shows a conventional trench capacitor
102
, comprising a polysilicon layer
132
having a plate portion
133
, and an oxide layer
142
extending into a trench
114
formed in a substrate
110
. Oxide layer
142
provides a dielectric layer between plate portion
133
and a depletion region
113
formed in substrate
110
around trench
114
. By orienting the capacitor “plates” in the vertical direction, trench capacitor
102
occupies significantly less IC die surface area than planar capacitor
101
. However, the irregular geometry of trench capacitor
102
significantly increases manufacturing complexity, thereby leading to increased cost and decreased reliability.
FIG. 1C
shows a conventional stacked capacitor
103
, comprising an oxide layer
144
sandwiched by an upper polysilicon layer
134
and an intermediate polysilicon layer
150
. Stacked capacitor
103
is formed over an NMOS transistor
160
. NMOS transistor
160
is not an essential component of stacked capacitor
103
, and can be replaced with other IC structures, such as bipolar transistors or resistive elements. NMOS transistor
160
comprises a polysilicon gate
162
and a gate oxide
164
formed over two n-type regions
120
in substrate
110
. An oxide layer
166
provides a surface insulating layer for NMOS transistor
160
. Intermediate polysilicon layer
150
is deposited over one of the n-type regions
120
of NMOS transistor
160
and a portion of oxide layer
166
. Intermediate polysilicon layer
150
also extends over a field oxide
124
that isolates NMOS transistor
160
from adjacent IC devices. Oxide layer
144
is formed over intermediate polysilicon layer
150
, and upper polysilicon layer
134
is deposited over oxide layer
144
to complete stacked capacitor
103
. The non-planar contours of upper polysilicon layer
134
and intermediate polysilicon layer
150
increase their effective surface areas, thereby increasing the capacitance of stacked capacitor
103
. Because stacked capacitor
103
is “stacked” over an existing IC structure, efficient IC die surface area utilization is provided. At the same time, the deep etch and subsequent step coverage issues of trench capacitor
102
are avoided. However, while stacked capacitor
103
is easier to produce than trench capacitor
102
, the formation of intermediate polysilicon layer
150
requires an additional polysilicon deposition step, thereby increasing overall manufacturing cost and cycle time for an IC including stacked capacitor
103
.
Due to variations inherent in semiconductor manufacturing processes, specific capacitance values are difficult to produce using the aforementioned conventional capacitance structures. The dielectric constant of an oxide layer can vary between production runs, and precise control of oxide layer thickness is difficult to achieve. Also, the non-planar configurations of the trench and stacked capacitors makes the areas of the polysilicon “plates” difficult to accurately control. Finally, during normal IC operation, temperature effects can change the material properties of the capacitive structures, leading to further variations in actual capacitance values. Therefore, conventional capacitive structures are ill-suited for situations requiring precise capacitance settings, such as delay lines and bandpass filters.
Accordingly, it is desirable to provide a capacitive structure in an IC that is compact, easily manufacturable, controllable, and adaptable to process and operating variations.
SUMMARY OF THE INVENTION
The present invention is directed towards apparatus and methods for creating capacitance in an integrated circuit (IC), overcoming the cost and accuracy limitations of conventional capacitive structures by utilizing controlled parasitic capacitance effects.
Typically, IC manufacturers attempt to eliminate parasitic (unwanted) capacitances in IC's. An IC comprises a variety of functional devices configured to perform specified sets of tasks. Dielectric material separates and isolates the functional devices from one another. Interconnects provide conductive paths between functional devices, thereby allowing signals to be transmitted from one functional device to another. When interconnects run parallel to one another, parasitic capacitances can be generated which impose undesirable effects on the signals travelling along the interconnects. Maintaining a large spacing between interconnects alleviates the problem, but the industry trend towards shrinking IC die sizes and increasing device densities makes such a technique unfeasible. Alternative methods such as multilevel, orthogonal placement of interconnects can reduce the effects of parasitic capacitances, but also increase manufacturing cost and complexity.
In an embodiment of the present invention, a conductive line is coupled to a bias control circuit. The conductive line is positioned parallel to an interconnect that electrically connects two IC devices within an integrated circuit. The bias control circuit applies a bias voltage to the parallel conductive line to induce a parasitic capacitance between the interconnect and the parallel conductive line. By making the parasitic capacitance equal to a desired capacitance, signals transmitted between the two IC devices along the interconnect can be delayed or filtered. The magnitude of the parasitic capacitance is controlled by the length of the parallel conductive line, the distance between the interconnect and the parallel conductive line, and the dielectric constant of the material between the interconnect and the parallel conductive line. Unlike an interconnect, which provides a conductive path between two or more IC devices, the parallel conductive line has no specific routing requirements, and can therefore be sized as necessary to provide the desired capacitance.
In another embodiment of the present invention, the bias control circuit comprises logic circuits to selectively bias the parallel conductive line to a desired voltage potential. Removal of the bias voltage from the parallel conductive line minimizes the capacitive path between the interconnect and the conductive line, thereby allowing the parasitic capacitance to be decoupled from the interconnect as desired.
In another embodiment of the present invention, multiple parallel conductive lines are placed along side the interconnect. By changing the number of the multiple parallel conductive lines to which the bias voltage is applied, the total capacitance coupled to the interconnect can be adjusted.
The present invention will be more fully understood in view of the following description and drawings.
REFERENCES:
patent: 4195282 (1980-03-01), Cameron
patent: 4937649 (1990-06-01), Shiba et al.
patent: 5148263 (1992-09-01), H
Bever Hoffman & Harms LLP
Cartier Lois D.
Crane Sara
Hoffman E. Eric
Xilinx , Inc.
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