Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-06-30
2001-01-30
Ngo, Chuong Dinh (Department: 2787)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S495000, C708S512000
Reexamination Certificate
active
06182100
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a method and system for data processing in general, and in particular to a method and system for performing a numerical estimation within a data processing system. Still more particularly, the present invention relates to a method and system for performing a logarithmic estimation within a data processing system.
2. Description of the Prior Art
A general purpose processor typically cannot perform a logarithmic function as efficiently as other mathematical operations such as additions, subtractions, and multiplications. A logarithmic function is likely to require many more processor cycles than a relatively processor cycle-consuming multiplication operation. The present disclosure provides a method for performing a logarithmic estimation, i.e., y=log
2
x, within a general purpose processor, where both the argument x and the result y are represented in a floating-point format. Without loss of generality, the floating-point format used for the purpose of illustration is the IEEE 754 format.
SUMMARY OF THE INVENTION
In view of the foregoing, it is therefore an object of the present invention to provide an improved method and system for data processing.
It is another object of the present invention to provide an improved method and system for performing a numerical estimation within a data processing system.
It is yet another object of the present invention to provide an improved method and system for performing a logarithmic estimation within a data processing system.
In accordance with a preferred embodiment of the present invention, a floating-point number includes a sign bit, multiple exponent bits, and a mantissa having an implied one and multiple fraction bits. A fraction part of an estimate is obtained via a table lookup utilizing the fraction bits of the floating-point number as input. An integer part of the estimate is obtained by converting the exponent bits to an unbiased representation. The integer part is then concatenated with the fraction part to form an intermediate result. Subsequently, the intermediate result is normalized to yield a mantissa, and an exponent part is produced based on the normalization. Finally, the exponent part is combined with the mantissa to form a floating-point result.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 4583180 (1986-04-01), Kmetz
patent: 5197024 (1993-03-01), Pickett
patent: 5365465 (1994-11-01), Larson
patent: 5524089 (1996-06-01), Takano
patent: 5570310 (1996-10-01), Smith
patent: 5652584 (1997-07-01), Yoon
Felsman Bradley Vaden Gunter & Dillon, LLP
International Business Machines - Corporation
Ngo Chuong Dinh
Salys Casimer K.
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