Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1998-09-28
2001-09-25
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S147000
Reexamination Certificate
active
06294936
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method and circuit for modulating a clock signal to spread its spectral energy over a band of frequencies.
BACKGROUND OF THE INVENTION
Electronic devices and systems such as microprocessors rely on clock signals to provide timing control. Such clock signals typically are based on a precision reference source such as a crystal oscillator. However, a crystal oscillator has a high Q value which results in the spectral energy of the clock signal being concentrated in a very narrow frequency band. The concentration of the energy at the clock frequency as well as its harmonics can lead to emission of electromagnetic interference (EMI) in excess of that permitted under applicable government regulations.
In certain electronic systems it is possible to dither or modulate the frequency of the clock signal in order to spread its spectral energy over a band of frequencies. The result of this spreading is a reduction of the energy of the clock or harmonics of the clock that might otherwise appear at any particular frequency or band. Such dithering of the clock signal facilitates compliance with the applicable government regulations.
Various approaches have been proposed for dithering a clock signal. For example, Hewlett-Packard has developed a technique for dithering the reference divider of a phase-locked loop (PLL) between values to create a modulation profile. U.S. Pat. No. 5,610,955 is directed to a variation of such technique that dithers both the reference divider and the feedback divider in a PLL in order to spread the resultant clock signal.
Although these approaches are successful in dithering the clock signal, there are however a number of disadvantages. For example, by dithering the feedback divider and/or reference divider the PLL is continually being driven out of lock. This means that the PLL loop dynamics (e.g., unity-gain frequency, damping, etc.) affect the performance of the resulting modulation. If the loop bandwidth is too narrow, the modulating profile is filtered. If the loop bandwidth is set up to be very wide, compromises must be made regarding the precision of the resulting output frequency and step size. As is known, wide loop bandwidths require small integers in the feedback divider path.
Another disadvantage of such conventional approaches is the requirement for significant additional hardware in order to implement clock dithering. For example, additional dividers are oftentimes necessary. Such additional hardware occupies chip area and increases the size and/or cost of the electronic device.
In view of the aforementioned shortcomings associated with conventional approaches, there is a strong need in the art for an improved method and circuit for dithering a clock signal. In particular, there is a strong need for a method and circuit for dithering a clock signal generated by a PLL which avoids continually driving the PLL out of lock. Moreover, there is a strong need in the art for a circuit and method for dithering a clock signal generated by a PLL which does not require significant additional hardware.
SUMMARY OF THE INVENTION
A spread-spectrum modulation method and circuit for a clock generator phase-locked loop is described herein in accordance with the present invention. In a preferred embodiment, the present invention involves injecting a dither signal into a PLL that is synchronized with and has the same period or fraction of the same period as the phase comparison performed within the PLL. Over such period, the phase error caused by the modulation will integrate to zero and hence avoid transmitting a disturbance to the loop. Consequently, the present invention avoids continually driving the PLL out of lock.
A particular embodiment of the present invention utilizes an output of the reference divider and/or feedback divider within the PLL to generate the dither signal. The dither signal will consequently have the same period or fraction of the same period as the comparison performed by the PLL phase comparator. The PLL phase comparator is a sampled-data system which has a zero in its transfer function for phase modulation at its input where the frequency of such phase modulation is equal to the sampling frequency or multiples thereof.
Moreover, such a configuration avoids the need for additional hardware which otherwise would increase the chip area and/or cost of the device. In a preferred embodiment, the reference divider and/or feedback divider is made up of a linear feedback shift register (LFSR). One or more stages of the LFSR provide an output which is used to generate the dither signal. In a preferred embodiment, the output from the LFSR exhibits a pseudo-random sequence. This tends to spread the frequency of the clock signal more randomly so as to avoid introducing undesirable harmonics.
According to a particular aspect of the present invention, a clock generator phase-locked loop is provided. The phase-locked loop includes a reference frequency source for providing a reference frequency; a phase comparator for producing a control signal based on a periodic comparison of a phase difference between respective signals provided to a first input and a second input of the phase comparator, the reference frequency being operatively coupled to the first input; a voltage-controlled oscillator for generating an output frequency based on the control signal provided by the phase comparator; a feedback divider which receives and divides the output frequency to provide a divider output which is operatively coupled to the second input of the phase comparator; and a modulation circuit for injecting a dither signal within the clock generator phase-locked loop to modulate the output frequency, a period of the dither signal being equal to or an integer fraction of a phase comparison period of the phase comparator.
According to another aspect of the invention, a clock generator phase-locked loop is provided which includes a reference frequency source for providing a reference frequency; a phase comparator for producing a control signal based on a phase difference between respective signals provided to a first input and a second input of the phase comparator, the reference frequency being operatively coupled to the first input; a voltage-controlled oscillator for generating an output frequency based on the control signal provided by the phase comparator; a feedback divider which receives and divides the output frequency to provide a divider output which is operatively coupled to the second input of the phase comparator; and a modulation circuit for injecting a dither signal within the clock generator phase-locked loop to modulate the output frequency, wherein at least one of a reference divider included in the reference frequency source and the feedback divider comprises a linear feedback shift register counter having a plurality of stages, and the modulation circuit comprises an output of at least one of the plurality of stages which is used to produce the dither signal.
In accordance with yet another aspect of the invention, a method is provided for dithering a clock generator phase-locked loop including a reference frequency source for providing a reference frequency, a phase comparator for producing a control signal based on a periodic comparison of a phase difference between respective signals provided to a first input and a second input of the phase comparator, the reference frequency being operatively coupled to the first input, a voltage-controlled oscillator for generating an output frequency based on the control signal provided by the phase comparator, and a feedback divider which receives and divides the output frequency to provide a divider output which is operatively coupled to the second input of the phase comparator. The method includes the step of injecting a dither signal within the clock generator phase-locked loop to modulate the output frequency, a period of the dither signal being equal to or an integer fraction of a phase comparison period of the phase comparator.
According to still another aspect
American Microsystems, Inc.
Lam Tuan T.
Renner , Otto, Boisselle & Sklar, LLP
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