Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-05-14
2001-09-11
Quach, T. N. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C438S624000, C438S786000
Reexamination Certificate
active
06288448
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductors and more specifically to interconnect barrier materials.
BACKGROUND ART
While manufacturing integrated circuits, after the individual devices such as the transistors have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This connection process is generally called “metalization”, and is performed using a number of different photolithographic and deposition techniques.
In one connection process, which is called a “dual damascene” technique, two channels of conductive materials, are positioned in vertically separated planes perpendicular to each other and interconnected by a vertical “via” at their closest point.
The first channel part of the dual damascene process starts with the placement of a first channel dielectric layer, which is typically an oxide layer of silicon dioxide (SiO
2
), over the semiconductor devices. A first damascene step photoresist is then placed over the oxide layer and is photolithographically processed to form the pattern of the first channels. An anisotropic oxide etch is then used to etch out the channel oxide layer to form the first channel openings. The damascene step photoresist is stripped and an thin adhesion/barrier layer is deposited to coat the walls of the first channel opening to ensure good adhesion and electrical contact of subsequent layers to the underlying semiconductor devices. The adhesion/barrier layer also improves the formation of subsequently deposited conductive material and acts as an adhesion/barrier material to prevent diffusion of such conductive material into the oxide layer and the semiconductor devices. A seed layer is then deposited on the adhesion/barrier material to act as the conductive material base, or “seed”, for subsequent conductive metal deposition. A first conductive material is then deposited on the seed layer and subjected to a chemical-mechanical polishing process which removes the various materials above the first channel oxide layer and damascenes the first conductive material in the first channel openings to form the first channels.
The via formation step of the dual damascene process starts with the deposition of a thin capping stop nitride layer of silicon nitride (SiN) over the first channels and the first channel oxide layer. The thin nitride layer acts to prevent diffusion of conductive material between channels. Subsequently, a separating oxide layer is deposited on the nitride layer. This is followed by deposition of a thin via nitride layer. Then a via step photoresist is used in a photolithographic process to designate round via areas over the first channels.
A nitride layer etch is then used to etch out the round via areas in the via nitride layer. The via step photoresist is then removed, or stripped. A second channel dielectric layer, which is typically an oxide layer of silicon dioxide, is then deposited over the via nitride layer and the exposed oxide in the via area of the via nitride layer. A second damascene step photoresist is placed over the second channel oxide layer and is photolithographically processed to form the pattern of the second channels. An anisotropic oxide etch is then used to etch the second channel oxide layer to form the second channel openings and, during the same etching process to etch the via areas down to the thin stop nitride layer above the first channels to form the via openings. The damascene photoresist is then removed, and a nitride layer etch process removes the nitride layer above the first channels in the via areas. An adhesion/barrier layer is then deposited to coat the via openings and the second channel openings. This is followed by a deposition of the second conductive material in the second channel openings and the via openings to form the second channel and the via. A second chemical-mechanical polishing process leaves the two vertically separated, horizontally perpendicular channels connected by cylindrical vias.
A subsequent nitride layer is then deposited as a capping layer or in preparation of multiple layers of channels.
The use of the dual damascene technique eliminates metal etch and dielectric gap fill steps typically used in the metalization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum to other metalization materials, such as copper, which are very difficult to etch.
One drawback of using copper is that copper diffuses rapidly through various materials. Unlike aluminum, copper also diffuses through dielectrics, such as oxides. When copper diffuses through dielectrics, it can cause damage to neighboring devices on the semiconductor substrate. To prevent diffusion, materials such as tantalum nitride (TaN), titanium nitride (TiN), or tungsten nitride (WN) are used as channel adhesion/barrier materials for copper.
For capping barriers between conductive channels, the preferred barrier material has been silicon nitride since it is a good barrier material. However, it has a high dielectric constant which means it tends to increase capacitance between channels and thus reduce semiconductor circuit speed.
However, even with the various types of barrier layers, copper is still subject to strong electro-migration, or movement of copper atoms under current which can lead to voids in the copper channels and vias. Copper also has poor surface adhesion. A solution, which would form a better capping material with better surface adhesion, which would mean less electro-migration, and with a lower dielectric constant, has been long sought. As the semiconductor industry is moving from aluminum to copper and other type of materials in order to obtain higher semiconductor circuit speeds, it is becoming more pressing that a solution be found.
DISCLOSURE OF THE INVENTION
The present invention provides a semiconductor interconnect barrier material having a lower dielectric constant, lower diffusion barrier characteristics, lower surface diffusion characteristics, and adhesion better than plain silicon nitride.
The present invention flier provides a semiconductor interconnect barrier material of boron silicon nitride having a lower dielectric constant, lower diffusion barrier characteristics, lower surface diffusion characteristics, and improved adhesion over conventional, plain silicon nitride.
The present invention further provides a semiconductor interconnect barrier material of boron silicon nitride having a lower dielectric constant, lower diffusion barrier characteristics, lower surface diffusion characteristics, and improved adhesion over conventional silicon nitride by modulating the boron to be boron rich near the conductive material.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5817572 (1998-10-01), Chiang et al.
patent: 5970373 (1999-10-01), Allen
patent: 0 394 054 A1 (1990-10-01), None
patent: 62-156822 (1987-07-01), None
Advanced Micro Devices , Inc.
Ishimaru Mikio
Quach T. N.
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