Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Isolation by pn junction only
Reexamination Certificate
2000-05-16
2001-09-18
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Isolation by pn junction only
C438S418000, C523S204000, C257S787000
Reexamination Certificate
active
06291309
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device that is implementable on a mother board or the like, and a method for manufacturing the same.
BACKGROUND ART
A conventional semiconductor device is assembled in a packaged condition. In addition, there is a case where a multichip module is configured by implementing a plurality of semiconductor chips on the substrate; however, causes increase in a defect rate in overall the module by accumulating the defect rate of respective semiconductor chips. For example, in the case where two semiconductor chips are implemented on a single module substrate, one defect memory chip causes overall defect of the module. Therefore, it is necessary handling to replace the defect semiconductor chip as a repairing work and discard the overall module as a defect product. Thus, a low yield and a low efficiency occur.
Quality inspection is simultaneously carried out in every unit of one or a plurality of the packed semiconductor chip and the semiconductor chip implemented on the module substrate. However, in the case where the total number of semiconductor chips to inspect is too many, a small number of semiconductor chips handlable by a single inspection decreases inspecting efficiency. Therefore, a method is desired to increase the inspection efficiency.
DISCLOSURE OF THE INVENTION
The present invention has been created in consideration of such point and has an object is to provide a semiconductor device and a method for manufacturing the same that can reduce defect rate in manufacturing the semiconductor device on which a plurality of semiconductor chips is implemented and can improve efficiency of inspection of respective semiconductor chips.
According to the present invention, the semiconductor device is formed by dividing semiconductor chips in a unit of a plurality according to the result of quality inspection of respective semiconductor chips after implementation of a plurality of other kind of semiconductor chips on the substrate to seal in a resin. Dividing semiconductor chips is carried out according to the result of quality inspection. When the semiconductor substrate comprising a plurality of semiconductor chips is manufactured, a defective part of semiconductor chips does not cause defect of overall semiconductor device. Thus, the defect rate in manufacturing the semiconductor device can be reduced. The semiconductor chip inspected for every substrate unit allows increase in inspection efficiency in comparison with inspection for individual a few semiconductor chips.
Particularly, it is preferable that a plurality of semiconductor chips is implemented on one surface of the substrate and respective semiconductor chips are inspected through a terminal formed on the other surface. In this case, the overall one substrate can be handled as one part to inspect a plurality of semiconductor chips implemented on the substrate. Thus, time for inspection can be reduced in comparison with the case where the inspection is carried out in a unit of the memory modules on which memories individually packed and a plurality of memory chips are implemented.
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patent: 6-61417 (1994-03-01), None
Ikeda Kouichi
Ikeda Takeshi
Dellett and Walters
Niebling John F.
Niigata Seimitsu Co., Ltd.
Stevenson Andre′ C.
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