Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2000-02-18
2001-06-12
Lee, Benny (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S310000
Reexamination Certificate
active
06246289
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a variable-gain multistage amplifier with broad bandwidth and reduced phase variations. More particularly, the invention relates to a programmable-gain multistage amplifier suitable for providing variable-gain stages in which the control range has a wide programmability scale with linearity characteristics expressed in dBs.
BACKGROUND OF THE INVENTION
It is known that analog multiplier structures, such as for example the Gilbert multiplier, an embodiment of which is shown in
FIG. 1
, are used in the production of variable-gain stages.
This circuit is of the fully differential type and entails the application of a differential signal IN− and IN+ which is converted from a voltage to a current so that the current in output from the bridge of the Gilbert cell is constituted by a static component due to the current provided by the current source Io plus a signal component due to the differential input voltage IN− and IN+ divided by the resistance R
E
.
The component of the current due to the differential input voltage is due to the transconductance of the input stage composed of the bipolar transistors
1
and
2
and specifically:
gm=gm/(1+gm/R
E
)
where gm is the transconductance of transistors
1
and
2
.
If now one assumes gm.R
E
to be much higher than 1, then gm is approximately equal to 1/R
E
.
A variable control voltage Vc is applied between the base of a transistor
4
and the bases of transistors
3
and
5
.
By solving mathematically the appropriate circuit equations, the gain of the circuit of
FIG. 1
is found to be equal to:
G=R
L
/R
E
.[1/(1+e
Vc/Vt
)]
where Vt is the threshold voltage of the transistors.
This expression can be used to show that when converting the gain into dBs by means of logarithms, in order to have gain linearity it is necessary to use a suitable control voltage Vc.
The maximum gain that can be obtained from the structure shown in
FIG. 1
is in any case R
L
/2/R
E
if the control voltage Vc is equal to 0.
This entails the fact that the upper limit of the gain has a maximum value beyond which it is impossible to go; said value can be obtained by decreasing the voltage Vc to 0, i.e., if the Gilbert multiplier is balanced.
Therefore, if one wishes to provide a high gain, the ratio between R
L
and R
E
must be given a high value, by increasing the value of the load resistor R
L
with respect to the resistor R
E
. In practical terms, this entails the fact that a very large parasitic pole is generated which is determined by the product of the resistance R
L
and of the parasitic capacitor C, so that an increase in gain is inevitably associated with a reduction in the band, and this is a severe drawback.
Another known embodiment of a variable-gain amplifier is given in the prior documents JP 02260906A and JP 01032509A, which substantially discloses a circuit as shown in
FIG. 2
, in which only half of the differential circuit is shown.
Said figure illustrates a differential input stage to which a differential signal IN is fed; said differential input stage is connected to a diode (the complete differential circuit is obviously connected to a pair of diodes) Q
3
, whose cathode terminal is connected to the base terminal of a bipolar transistor Q
4
, in which the collector terminal is connected to the supply voltage by interposing a load resistor R
L
and the emitter terminal is connected to a current source I
2
.
The input signal IN is fed to a bipolar transistor Q
1
, whose collector terminal is connected to the cathode terminal of the diode Q
3
and whose emitter terminal is connected to a resistor R
E
, which is in turn connected to a current source
2
I
1
.
Parasitic capacitors C
L
are respectively connected between the collector terminal of the transistor Q
4
and the resistor R
L
(parasitic capacitor C
L
) and between the collector terminal of the transistor Q
1
and the cathode of the diode Q
3
(parasitic capacitor C
p
).
The voltage gain can be obtained from this circuit configuration and is given by:
A
v
=
Vout
Vin
=
R
1
R
E
·
I
2
I
1
which is obtained, as a first approximation, by ignoring the effect of the input transistor Q
1
.
Frequency response is instead given by the chart shown in
FIG. 3
, in which the first pole of the transfer function is equal to:
1/R
L
C
L
.2&pgr;
while the second pole is determined mainly by the contribution of the parasitic capacitor C
p
to the node V
1
, plus all the limitations determined by the transistors Q
1
, Q
4
and Q
3
.
SUMMARY OF THE INVENTION
The present invention provides a programmable-gain multistage amplifier that has a broad bandwidth and reduced phase variations.
The present invention also provides a variable-gain amplifier that has a wide programmability range.
The present invention further provides a variable-gain amplifier that is highly reliable and relatively easy to manufacture at competitive costs.
The foregoing are achieved by a programmable-gain multistage amplifier with broad bandwidth and reduced phase variations, that includes a differential input stage biased by a first current source and to which a differential voltage signal is fed, the stage being connected to a pair of diodes in which the cathode terminals are connected to respective bipolar transistors, which are biased by a second current source, and in which the collector terminals are connected to load resistors, the differential output of the amplifier being provided at the collector terminals of the bipolar transistors; and further including two circuit branches, each of which is constituted by a bipolar transistor and by a third current source, which is respectively connected to the collector terminal and emitter terminal of the bipolar transistor, in which the base terminal receives the differential voltage signal and the collector terminal is connected to the cathode terminal of a respective one of the two diodes, the circuit branches being mutually connected by means of a pair of capacitors.
REFERENCES:
patent: 4344044 (1982-08-01), Harford
patent: 5057788 (1991-10-01), Ushida et al.
patent: 5461342 (1995-10-01), Crabtree
patent: 5742199 (1998-04-01), Shoji et al.
patent: 5994959 (1999-11-01), Ainsworth
patent: 59131210 (1984-07-01), None
patent: 01032509 (1989-02-01), None
patent: 02260906 (1990-10-01), None
patent: WO 98/49769 (1998-11-01), None
Marchese Stefano
Pisati Valerio
Portaluri Salvatore
Savo Alessandro
Choe Henry
Galanthay Theodore E.
Lee Benny
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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