Method for designing a semiconductor integrated circuit

Details Method for designing a semiconductor integrated circuit Method for designing a semiconductor integrated circuit

1996-03-15

1998-10-20

Tsai, Jey

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

438129, H01L 2182

Patent

active

058245707

ABSTRACT:
A semiconductor integrated circuit capabling of reducing a chip area by facilitating optimization of a chip layout and a method for designing the same has been provided. For given gate level connection description, use cell information designating gates which should be designed by employing the cell patterns prepared in advance is generated. When the gate level connection description is developed into the transistor level, hybrid connection description including mixedly transistor level and gate level is then generated by employing the cell patterns relative to the gates which being designated by the use cell information and by developing gates which being not designated by the use cell information into transistor level. A layout is then designed based on the hybrid connection description including mixedly the transistor level and the gate level.

REFERENCES:
patent: 4786613 (1988-11-01), Gould et al.
patent: 5348902 (1994-09-01), Shimada et al.
patent: 5459340 (1995-10-01), Anderson et al.
patent: 5563801 (1996-10-01), Lee et al.

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