Nonvolatile semiconductor memory and read method

Details Nonvolatile semiconductor memory and read method Nonvolatile semiconductor memory and read method

2000-02-03

2001-04-24

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Multiple values

C365S185240

Reexamination Certificate

active

06222763

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a technique, which is particularly applicable to a read method for multiple-value information in a semiconductor memory and, moreover, is effective for a nonvolatile semiconductor memory. More particularly the invention is applicable to a technique which may be effectively used for a nonvolatile memory (hereafter referred to as a flash memory) to electrically simultaneously erase a plurality of stored pieces of information.
A flash memory uses a nonvolatile memory cell having a control gate and a floating gate as a memory cell. It is possible to constitute the memory cell of one transistor. In the case of a write operation of the flash memory, as shown in
FIG. 16
, a state in which the threshold voltage is low (logic “0”) is set up by setting the drain region of a nonvolatile memory cell at approx. 5 V (volt) and a word line connected with a control gate CG at approx. −11 V and, thereby, extracting electric charges from a floating gate FG by means of a tunnel current. In the case of an erase operation, as shown in
FIG. 17
, a state in which the threshold voltage is high (logic “1”) is set up by setting a well region, drain region and source region at approximately 0V and the control gate CG to a high voltage, such as 16V, thereby generating a tunnel current, and injecting negative electric charges into the floating gate CG. During the read operation, it is judged that the data stored in a memory cell through which current flows is “0” and a memory cell through which no current flows is “1” by setting the control gate at an intermediate voltage between a high threshold and a low threshold and detecting whether current flows or not. Thereby, one-bit of data is stored in one memory cell.
A technique has been proposed, which is related to the so-called multiple-value memory, for storing data of two bits or more in one memory cell in order to increase the memory capacity. An invention related to the multiple-value memory is disclosed in Japanese Patent Application No. 14031/1995, etc.
Such a multiple-value memory stores information by controlling the amount of electric charges to be injected into a floating gate, thereby stepwise changing thresholds to 1 V, 2V, 3V, . . . , and making information of a plurality of bits correspond to each threshold value.
FIG. 18
shows a threshold value distribution state when storing information by dividing one memory cell into four threshold value states (this will be referred to as four-value state in this specification). It is difficult to accurately control the threshold value of a memory cell to a predetermined value for a write operation, and therefore, as shown in
FIG. 18
, a normal distribution is established around each target threshold voltage. To read data, voltages corresponding to the valleys of the threshold value distributions are read, set as VRW
1
, VRW
2
, and VRW
3
, and applied to a control gate through a word line. In this case, the drain is set at a potential, such as 1V, and the source is set at a potential, such as 0V. The bit-line precharging method can be used for the setting of the drain voltage.
Table 1 shows the results of reading data from memory cells belonging to the threshold value distributions A, B, C, and D by using the above read voltages VRW
1
, VRW
2
, and VRW
3
(VRW
1
<VRW
2
<VRW
3
). Because the memory cell belonging to the threshold value distribution A has the highest threshold value, no current flows even if any one of VRW
1
, VRW
2
, and VRW
3
is applied. Therefore, the read result is “1”. In the case of the memory cell belonging to the threshold value distribution B, the read result is “1” because no current flows when VRW
1
or VRW
2
is applied. However, when VRW
3
is applied, the read result is “0” because current flows. In the case of the memory cell belonging to the threshold value distribution C, the read result is “1” because no current flows when VRW
1
is applied. However, when VRW
2
or VRW
3
is applied, the read result is “0” because current flows. In the case of the memory cell belonging to the threshold value distribution D, the read result is always “0” in any case because current flows if any one of VRW
1
, VRW
2
, and VRW
3
is applied. Though a case of a four-value memory has been described above, the same holds theoretically for eight- and sixteen-value memories.
TABLE 1
Memory A
Memory B
Memory C
Memory D
VRW3
1
0
0
0
VRW2
1
1
0
0
VRW1
1
1
1
0
SUMMARY OF THE INVENTION
In the case of a four-value memory, it is possible to store two-bit information because any one of four threshold values can be set in one memory cell. In the case of a conventional two-value memory for storing one-bit of information in one memory, the read operation is performed once because two threshold values are judged to obtain one-bit of information. In the case of a four-value memory, however, it is necessary to perform the read operation three times by changing the potentials of a word line in order to obtain two-bit information. Therefore, simply saying, a problem arises that the read time is three times larger than that of a two-value memory and the power consumption for the read operation also increases three times.
Moreover, in the case of a nonvolatile memory using a MOSFET having a floating gate as a memory cell, a phenomenon (hereafter referred to as read disturb) occurs wherein a small amount of hot electrons generated in the read operation are injected into the floating gate when the read operation is repeated, and, thereby, the threshold value is raised. Therefore, a drawback occurs in that the threshold value fluctuation in a memory cell increases as the read frequency increases, exceeds the read level in the worst case and, resultingly, the stored data may be changed.
Moreover, as described above, it is necessary to apply the earthing potential Vss (0 V) to the source of a memory cell during the read operation. As shown in
FIG. 19
, a power supply line (ground line) GL for the purpose is extended from the external terminal (ground pin) GND of a chip to each memory cell MC in a memory array M-ARY. The power supply line is generally constituted of a metal wiring layer made of, for example, aluminum. However, at a portion where the aluminum wiring is used for another signal line, such as a bit line, the earthing potential may be applied to each memory cell MC through a diffusion layer having a large resistance value. In this case, as shown in
FIG. 19
, the ground line length differs between the memory cell closest to the ground GND and the memory cell farthest from the ground GND. For example, the wiring of the diffusion layer has a resistance value of hundreds of m&OHgr; per &mgr;m and even a metal wiring has a resistance value of approx. 100 &OHgr;. Therefore, a portion between the ground pin and the memory cell farthest from the ground pin GND has hundreds; to thousands of &OHgr;. Therefore, when a current flows from a memory cell during a read operation, the source potential rises and, thereby, the source potential greatly differs between the memory cell closest to the ground pin and the memory cell farthest from the ground pin. If the read current is 3 mA and the ground resistance differs by 100 &OHgr;, a difference of 0.3 V occurs in the source potential.
In the case of a memory cell, the drain current logarithmically changes nearby the threshold value as known from the characteristics of a MOSFET. Therefore, when the source potential rises and the voltage between the gate and source lowers, the current decreases by one-tenth to one-hundredth. In this case, if the characteristics of memory cells belonging to the distributions B and D in
FIG. 18
have the characteristics shown by b and d in
FIG. 20
, a sufficient amount of current can be ensured even if the source potential slightly rises when applying a voltage of 5 V to each gate because the memory cell D is in a completely saturated region. However, because the memory cell B is only slightly saturated, it is found that the current is greatly decreased due to a

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