Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1999-11-16
2001-09-25
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S239000, C438S253000, C438S254000, C438S255000, C438S393000, C438S397000
Reexamination Certificate
active
06294437
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88117960, filed Oct. 18, 1999.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing dynamic random access memory (DRAM). More particularly, the present invention relates to a method of manufacturing a crown-shaped DRAM capacitor.
2. Description of the Related Art
A capacitor is a principle component in each dynamic random access memory (DRAM) cell. The amount of electric charges stored in a capacitor can affect its susceptibility to external interference such as alpha particles and hence soft errors. In addition, refreshing frequency also depends on the storage capacity of a capacitor.
A charge storage problem is accentuated by newer generation of memories whose feature dimensions are reduced to below 0.25 &mgr;m. To increase the capacitance of a capacitor in a smaller area, effective surface of the capacitor must be increased. The formation of a crown-shaped structure is one of the methods to increase the surface area of a capacitor. To increase capacitance even further, especially for fabricating semiconductor devices having a feature dimension smaller than 0.18 &mgr;m, hemispherical silicon grains (HSGs) are also formed on the interior and exterior sidewalls of the crown-shaped structure.
In general, a capacitor with a crown-shaped structure is formed by forming a silicon oxide layer and a silicon nitride layer in sequence over a substrate. A polysilicon plug is next formed through the silicon oxide layer and the silicon nitride layer. A second silicon oxide layer is formed over the silicon nitride layer and the polysilicon plug, and then a crown-shaped opening is formed in the second silicon oxide layer. A doped amorphous silicon layer conformal to the sidewalls of the crown-shaped opening as well as the second silicon oxide layer is formed. Chemical-mechanical polishing (CMP) is next carried out to remove the doped amorphous silicon layer above the second silicon oxide layer so that the lower electrodes of different capacitors are isolated from each other. A portion of the second silicon oxide layer is removed so that an oxide layer with a definite thickness remains on top of the silicon nitride layer as a protective layer. The silicon nitride layer needs to be protected because hemispherical silicon grains (HSGs) may also form over the silicon nitride layer when HSGs are formed over the doped amorphous silicon layer. If a layer of HSGs is formed on the silicon nitride layer, the lower electrode of different capacitor may be short-circuited.
In the aforementioned method, the second silicon oxide layer must be etched twice in two separate etching operations. Since there is no reference etching point layer for determining the end of the operation, the first etching operation can only be arbitrarily controlled by etching duration. In general, the first etching of the second silicon oxide layer is conducted using diluted hydrofluoric acid (DHF) or hydrogen fluoride steam. If diluted hydrofluoric acid is used to carry out the etching, silicon wafers are normally inserted vertically into a bath of the liquid. Consequently, the portion of the wafer dipped into the bath the earliest will remain in the bath for the longest period. Moreover, different portions of the wafer will be immersed inside the bath for a different duration. Hence, the resulting thickness of the second silicon oxide layer on a wafer will vary from place to place, and the capacitance of each capacitor will be different, with serious consequences.
On the other hand, if hydrogen fluoride vapor steam is used to carry out the etching, some non-volatile residues may adhere to the surface of the wafer. These residues are difficult to remove and may lead to the formation of defects on the wafer.
SUMMARY OF THE INVENTION
The invention provides a method of manufacturing a crown-shaped DRAM capacitor. A silicon oxide layer and a silicon nitride layer are sequentially formed over a substrate. A conductive plug is formed, passing through the silicon oxide layer and the silicon nitride layer. A first and a second dielectric layer are sequentially formed over the silicon nitride layer and the conductive plug. A first opening that exposes the conductive plug and a portion of the silicon nitride layer surrounding the plug is formed through the second and the first dielectric layer. A doped amorphous silicon layer conformal to the substrate profile is formed. The doped amorphous silicon layer above the second dielectric layer is removed. The second dielectric layer is next removed, and then hemispherical silicon grains (HSGs) are grown over the exposed surface of the doped amorphous silicon layer. The first dielectric layer is removed. Finally, a third dielectric layer and a conductive layer are sequentially formed over the substrate.
The first dielectric layer can be a silicon oxide layer, and the second dielectric layer can be a borophosphosilicate glass layer, for example. The third dielectric layer can be, for example, a composite layer that includes a silicon nitride layer and a silicon oxide layer.
In this invention, the conventional second silicon oxide layer is replaced by the first and the second dielectric layer. Utilizing the difference in material properties between the first and the second dielectric layer, the first dielectric layer can function as an etching stop layer in the etching of the second dielectric layer. The first dielectric layer also serves as a protective layer for the silicon nitride layer, only to be removed after HSGs are grown over the exposed doped amorphous silicon layer.
In brief. the first dielectric layer not only functions as an etching stop layer for etching the second dielectric layer, but also prevents the growth of hemispherical silicon grains over the silicon nitride layer. Hence, capacitors with the same design will have identical capacitance and wafer yield will greatly increase.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5597756 (1997-01-01), Fazan et al.
patent: 6054347 (2000-04-01), Lin
patent: 6096653 (2000-08-01), Tu et al.
Huang Jiawei
J. C. Patents
Nguyen Ha Tran
Niebling John F.
Taiwan Semiconductor Manufacturing Co. Ltd.
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