Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Phase shift by less than period of input
Reexamination Certificate
1999-06-10
2001-08-14
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Phase shift by less than period of input
C327S245000, C365S233100
Reexamination Certificate
active
06275084
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to an integrated circuit and more particularly to an integrated circuit with phase modulated input and output circuits.
BACKGROUND OF THE INVENTION
Present complementary metal oxide semiconductor (CMOS) synchronous dynamic random access memory (SDRAM) circuits are frequently used for main memory in a variety of applications including desk top and portable computer systems. Advances in system technology require ever increasing clock rates and memory bus widths to achieve high data rates. Both of these methods, however, are subject to practical limitations. Increased clock rates increase system cost due to a need to reduce parasitic loading. Increased memory bus widths fulrther increase system cost by increasing memory package pin counts, thereby increasing memory package size and a required number of printed circuit board traces.
A proposed solution to these problems was presented by K. Nogami & A. El Gamal, A CMOS 160 Mb/s Phase Modulation I/O Interface Circuit, ISSCC Digest of Technical Papers, February 1994 at
108
. Nogami et al. present a circuit for transmitting and receiving multiple data bits over each input/output (I/O) pin in a single clock cycle. Each clock cycle is divided into 2
N
phases or respective time slots. A logic state of each of N data bits corresponding to a single I/O pin, determines the respective time slot during which a data signal is transmitted or received. Thus, multiple data bits are phase modulated and simultaneously transmitted or received during a single clock cycle.
Nogami et al. use a voltage controlled oscillator (VCO) and phase locked loop (PLL) circuit to maintain stable phase positions with variations in temperature, supply voltage and the manufacturing process. The VCO and PLL circuits, however, increase circuit complexity and power consumption. Moreover, Nogamni et al. require a periodic reference cycle within data cycles compensate for VCO frequency drift. This periodic reference cycle interrupts data transmission and imposes an additional task on the system processor or memory controller. Finally, Nogami et al. require synchronization with a system clock. This imposes a significant limitation on large circuits such as memory systems, since propagation delay of the system clock may be substantially different from a propagation delay along an I/O bus.
SUMMARY OF THE INVENTION
These problems are resolved by a circuit comprising a delay circuit coupled to receive a clock signal having a period and a reference signal. The delay circuit produces a series of phase signals within a time no greater than the period. Each phase signal has a respective time with respect to the reference signal. A data circuit, responsive to a plurality of N data signals and at least one phase signal produces an output signal after the respective time of the at least one phase signal.
The present invention provides phase modulated I/O without VCO and PLL circuit complexity and power consumption. Multiple data bits are passed through each I/O terminal in a single clock cycle to increase the data rate.
REFERENCES:
patent: 4589099 (1986-05-01), Laffitte et al.
patent: 5321369 (1994-06-01), Wolaver
patent: 5486783 (1996-01-01), Baumert et al.
patent: 5886946 (1999-03-01), Ooishi
patent: 5995441 (1999-11-01), Kato et al.
“A CMOS 160Mb/s Phase Modulation I/O Interface Circuit”, Nogami, et al., ISSCC94, Session 6, Clock and Data Recovery, Paper TA 6.1, Digest of Technical Papers, 2 sheets, 1994.
Brady III W. James
Callahan Timothy P.
Luu An T.
Rountree Robert N.
Telecky , Jr. Frederick J.
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