Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Utility Patent
1997-12-30
2001-01-02
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S318000, C327S427000
Utility Patent
active
06169439
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates, in general to power metal oxide semiconductor (MOS) devices and, more particularly to a current limited power MOSFET device with improved safe operating area.
2. Relevant Background
Due to their ability to rapidly switch high currents and high voltages, power metal oxide semiconductor (MOS) devices are gaining popularity in power switching circuits. Power switches are generally defined as switches capable of handling greater than 0.5 amperes current and voltage ranges from 25 volts to greater than 1 kV. Power MOSFET devices are available to handle currents of tens and even hundreds of amperes.
Power MOSFET devices are widely used in the automotive industry for engine controllers, lamp drivers, antilock brake systems, and the like. In these applications the power MOSFET devices are incorporated into circuit boards and circuit module subassemblies. These subassemblies are then installed and assembled into finished products. These subassemblies may be exposed to severe electrical stress during assembly from such external sources as arc welders used to fasten body components. Such stress may cause power MOSFET devices to experience drain-source voltages in excess of their rated drain-source breakdown voltage(BVdss).
Power MOSFET devices are also used to switch inductive loads such as motors and transformers. When the power MOSFET device is switched off, the energy stored in the inductor will force the drain voltage of the power MOSFET to rise rapidly above the supply voltage. If no limiting means are employed, this rise will continue until the drain-source avalanche voltage of the power MOSFET is reached whereupon the energy stored in the inductor will dissipate in the power MOSFET during device avalanche. Such dissipation can cause avalanche stress induced failure of the power MOSFET. Although the inductive load can be dissipated by external devices, it is very advantageous for the power MOSFET device to be able to dissipate the stored inductive energy without using external circuits.
It is well known that power MOSFET devices provide more safe operating area if the gate is turned on prior to the MOSFET device reaching its drain-source breakdown voltage. The safe operating area (SOA) when the gate is turned on is referred to as the forward bias safe operating area or FBSOA. In FBSOA mode current can be dissipated throughout the body of the MOSFET device using channel structures within in the device that are optimized for maximum current flow. Because the on resistance under forward bias tends to increase with temperature, the device is self stabilizing and resists the occurrence of hotspots that can cause catastrophic destruction of the device.
However, if the MOSFET device reaches its BVDSS, current and breakdown flows in highly localized areas about the surface of the chip often at the edge of the MOSFET device. This causes “hotspots” of current in which resistance to current flow decreases with increasing temperature. Hence, device destruction occurs rapidly when a reverse breakdown voltage occurs. This is called reverse bias safe operating area or RBSOA.
One method of protecting against RBSOA failures involves diverting a small fraction of the drain-source energy to the power MOSFET gate by means of a drain-gate clamp diode whose avalanche voltage is about two to three volts less than the avalanche voltage of the power MOSFET. When rising drain voltage reaches the avalanche voltage of the drain-gate clamp diode, the resulting avalanche current develops a voltage across a gate-source termination resistor that turns on the power MOSFET, effectively clamping its drain to the sum of the drain-gate diode avalanche voltage and the voltage across the gate-source termination resistor. In this manner, the MOSFET acts as its own clamp, and dissipates the excessive energy in the less stressful forward biased mode. A second blocking diode is used in back-to-back configuration with the drain-gate clamp diode to enable the gate-source voltage in normal operation to exceed the drain-source voltage.
Some state of the art power MOSFET devices include current limit circuitry to protect the load driven by the power MOSFET device from undesirable current levels. Several current limit circuits are known and power MOSFET devices are available with current limit circuitry integrated monolithically with the power MOSFET device. Essentially, most current limit devices include structures that tend to reduce the gate voltage when a current limit is reached. The limit current can be detected by a current mirror transistor connected in parallel with the high current power MOSFET device. The detected current typically drives a transistor that drains charge from the MOSFET gate when the current limit is reached. By removing charge from the gate upon reaching the current limit, the main power device is forced into saturation in which case a power MOSFET device acts substantially as a constant current source.
Current limit devices work relatively well in FBSOA mode. While the current flowing through the devices is less than the current limit, the transient voltage generated by turning off an inductive load can be dissipated in FBSOA mode. However, when the current limit is reached, the current limit circuitry tends to pull the gate voltage down by directing charge away from the power MOSFET gate. This action tends to increase the current flowing through a drain-gate clamp diode.
The increased current through the drain-gate clamp diode increases the breakdown voltage of the drain-gate clamp diode beyond the breakdown voltage of the drain-source diode within the field effect transistor. When the inductor transient voltage increases beyond the drain-source breakdown voltage, the device enters reverse bias SOA mode and destructive failure occurs rapidly. The need exists for a power MOSFET device with both current limit capability to protect the loads and an ability to disable the current limit circuitry when the device must dissipate a large stored inductive energy.
SUMMARY OF THE INVENTION
Briefly stated, the present invention involves an integrated circuit having a protected output field effect transistor (FET). A drain-gate clamp circuit is coupled to divert charge from the power FET drain electrode to the power FET gate electrode when excessive drain-source voltage is present. A drain-source current limit circuit is coupled to divert charge from the power FET gate electrode to the power FET source electrode when a preselected drain-source current is achieved. A current limit inhibit circuit is coupled between the current limit circuit and the power FET gate electrode, and having a control electrode coupled to the drain-gate clamp circuit. The current limit inhibit circuit disables the current limit circuit when charge flows in the drain-gate clamp circuit.
In another aspect, a method of protecting a field effect transistor in accordance with the present invention includes the steps of sensing when a drain current in the FET is at a preselected current level and sensing when a drain-source voltage is above a preselected voltage level. The gate charge is moderated to maintain the drain current at or below the preselected level until the preselected voltage level is sensed. In response to sensing the preselected voltage level, the moderation of the gate charge is interrupted until the preselected voltage is no longer sensed. In this manner, the FET can dissipate energy caused by the voltage in excess of the preselected voltage level in a forward biased mode.
These and other objects, features and advantages of the invention will be apparent to those skilled in the art from the following detailed description of the invention, when read in conjunction with the accompanying drawings and appended claims.
REFERENCES:
patent: 5001373 (1991-03-01), Bator et al.
patent: 5272392 (1993-12-01), Wong et al.
patent: 5272399 (1993-12-01), Tihani et al.
patent: 5561391 (1996-10-01), Wellnitz et al.
patent: 5608595 (1997-03-01), Gourab et al
Baldwin David J.
Teggatz Rex M.
Teggatz Ross
Brady III Wade James
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Zweizig Jeffrey
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