Floating point processor architecture which performs subtraction

Details Floating point processor architecture which performs subtraction Floating point processor architecture which performs subtraction

1979-06-04

1981-08-04

Malzahn, David H.

Boots, shoes, and leggings

G06F 750

Patent

active

042825822

ABSTRACT:
There is provided a circuit and method for subtracting floating point numbers which are represented by binary bits. In this circuit, the smaller number (minuend) in one register is arranged so that the complement thereof is denormalized and added to the subtrahend (i.e. larger number) and the result of the addition is returned to the original register. At that time, the signal stored in the register is renormalized. In this circuit, the number of guard bits required to guarantee round off accuracy is only two.

REFERENCES:
patent: 3551665 (1970-12-01), Powers et al.
patent: 3697734 (1972-10-01), Booth et al.
patent: 3699326 (1972-10-01), Kindell et al.
patent: 4075704 (1978-02-01), O'Leary
Frye "Floating Point Guard Digit" IBM Tech. Disclosure Bulletin vol. 10 No. 10 Mar. 1968 pp. 1523-1524.
Sofer et al., "Parallel Pipeline Organization of Execution Unit" IBM Technical Disclosure Bulletin vol. 14 No. 10 Mar. l972 pp. 2930-2033.

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