Analog multiplier with thermally compensated gain

Details Analog multiplier with thermally compensated gain Analog multiplier with thermally compensated gain

2000-01-04

2001-03-06

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific input to output function

Combining of plural signals

C327S359000

Reexamination Certificate

active

06198333

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to analog multipliers and, more specifically, to pseudo-four-quadrant analog multipliers requiring a reduced thermal sensitivity such as required in the multiplication stage of a preamplifier of a cathode-ray tube.
DESCRIPTION OF THE RELATED ART
In analog-signal processing the need often arises for a circuit that takes two analog input signals and produces an output signal proportional in magnitude to their product. Such a circuit is called an analog multiplier. The term “four-quadrant” multiplier is well known in the art, and refers to a circuit capable of multiplying two signed analog signals. Four-quadrant analog multipliers are fundamental building blocks for many circuit applications, e.g. phase detectors in phase-locked loops and frequency translators. Four-quadrant analog multipliers are specially useful in applications such as audio and video signal processing and adaptive filters.
A number of diverse circuit techniques have been developed to generate an output signal that is proportional in magnitude to the product of two input signals. One technique which is also readily suited to monolithic circuits depends upon the variations in transconductance in differential stages to perform the four-quadrant multiplication. When constructed from bipolar transistors, the technique makes use of the dependence of the transistor transconductance on the emitter current bias.
One analog multiplier is the so-called “Gilbert Cell”, described in B. Gilbert, “A precise Four-Quadrant Multiplier with Subnanosecond Response”, IEEE J. Solid-State Circuits, Vol. SC-3, 373-380 (December 1968). The Gilbert Cell is constructed using bipolar transistors and relies on variations in transconductance of three differential stages to perform the multiplication. The Gilbert Cell however, has a very limited input dynamic range.
FIG. 1
illustrates a transistor schematic representation of an analog multiplier
100
known in the prior art. The circuit employs variable-transconductance technique to generate an output voltage V
M
which is the product of the three input voltages, namely V
x
, V
y
and Video. Output voltage V
M
is applied to the input terminal of output buffer
101
, which has a gain of “−10” and which generates output voltage V
out
at its output terminal.
The first disadvantage of analog multiplier
100
of
FIG. 1
is that it is highly sensitive to temperature variation. From
FIG. 1
it can be seen by inspection that
I
1
−I
2
=2*(V
x
−2)/R
x2
  (1)
I
3
−I
4
=2*(V
y
−2)/R
y2
  (2)
V
1
−(I
1
−I
2
)*R
x1
=2*(R
x1
/R
x2
)*(V
x
−2)  (3)
V
2
=(I
3
−I
4
)*R
y1
=2*(R
y1
/R
y2
)*(V
y
−2)  (4)
The collector currents I
qc1
, I
qc2
, I
qd1
and I
qd2
are related to voltages V
1
and V
2
according to the following equations:
V
1
=V
T
*ln(I
qd1
/I
qd2
)  (5)
V
2
=V
T
*ln(I
qc1
/I
qc2
)  (6)
V
T
is the thermal voltage and is equal to kT/q which is approximately equal to 26 mv at
300° K, where
k=Boltzmann's constant
T=Temperature (in ° K)
q=electric charge of an electron
The multiplier output voltage V
M
is directly proportional to the terms ln(I
qd1
/I
qd2
) and ln(I
qc1
/I
qc2
). Consequently, variations in these two ratios directly affect the value of the multiplier output voltage. To keep these ratios constant over temperature, voltages V
1
and V
2
must follow the temperature variations of V
T
. Since the resistance of resistors R
x1
and R
x2
have a similar temperature dependence, the ratio R
x1
/R
x2
and consequently, output voltage V
1
have a minimal temperature sensitivity as can be seen from equation (3). Similarly, voltage V
2
has a negligible temperature dependence. Therefore, changes in temperature directly affect multiplier output voltage V
M
through the thermal voltage term V
T
.
FIG. 2
illustrates a simulation result of the variation in output voltage V
M
of multiplier
100
of
FIG. 1
as the input voltages V
x
and V
y
are varied. For this simulation, input voltages V
x
and V
y
are set equal to one another and are swept from 0 volt to 4 volts as shown along the x-axis, and input voltage Video is kept constant at 0.7 volts. The y-axis shows the difference in the output voltage V
M
as the input voltages V
x
and V
y
are varied. For proper operation, it is required that output voltage V
M
of multiplier
100
rise with increasing temperature when input voltages V
x
and V
y
are above 2 volts. Similarly, it is required that output voltage V
M
of multiplier
100
fall with decreasing temperature when input voltages V
x
and V
y
are below 2 volts.
FIG. 3
shows the change in output voltage V
out
of
FIG. 1
when temperature changes from 0° C. to 85° C., for the condition when input voltages V
X
and V
y
are both equal to 3 volts and input voltage Video is at 0.7 volts. From
FIG. 3
it can be seen that output voltage V
out
increases by 620 mv as temperature changes from 0° C. to 85° C. rendering this multiplier ineffective for many applications.
The second disadvantage of multiplier
100
of
FIG. 2
is that it has a relatively small input dynamic range above which the multiplier would not behave in a linear fashion.
FIG. 4
illustrates another analog multiplier circuit
200
known in the prior art. Output voltage V
M
of multiplier
200
is applied to the input terminal of output buffer
201
which has a gain of “−10” and which generates output voltage V
out
at its output terminal. In analog multiplier circuit
200
, diode-connected transistor Q
a
is placed between transistor Q
aa
and the supply voltage V
CM1
, and diode-connected transistor Q
b
is placed between transistor Q
bb
and the supply voltage V
CM1
. By inspection, it can be seen that
V
1
=V
T
*ln(I
a
/I
b
)  (7)
I
a
−I
b
=2*(V
x
−2)/R
x2
  (8)
Resistor R
x2
has a positive temperature coefficient. Therefore, as temperature increases the resistance of the resistor R
x2
increases, thus causing a reduction in the current term (I
a
−I
b
) and in the ln(I
a
/I
b
) term of equation (8) above. The reduction in the term ln(I
a
/I
b
) decreases voltage V
1
's dependence on voltage V
T
, which is undesirable.
FIG. 5
shows an increase of 365 mv in the output voltage V
out
of
FIG. 4
when input voltages V
x
and V
y
are each set to 3 volts, input voltage Video is at 0.7 volts, and temperature is changed from 0° C. to 85° C. Although circuit
200
of
FIG. 4
provides an improvement over circuit
100
of
FIG. 1
, the multiplier output voltage shift for the given temperature range is too great, thereby rendering use of this multiplier inadequate for many applications.
The second disadvantage of the multiplier of
FIG. 4
is that it suffers from ringing problems at its output terminal. The emitter terminals of transistors Q
a
and Q
b
each have a high impedance when the input voltage V
x
or V
y
is either at 0 or 4 volts, making the output signal of the multiplier susceptible to ringing effect.
SUMMARY
An analog multiplier for multiplying three voltage signals utilizes circuitry for keeping the multiplier output voltage reasonably constant over temperature. Two semi-logarithmic voltage generating stages are used to provide input voltages to two variable transconductance circuits forming the last stage of the multiplier. Two differential stages receive level-shifted multiplier input voltages and convert them to currents. The multiplier includes devices for eliminating ringing at the output of the multiplier.
In accordance with the present invention the analog multiplier has a reduced temperature dependence. The multiplier has a wide dynamic range and is immune to ringing effect.


REFERENCES:
patent: 4019118 (1977-04-01), Harwood
patent: 5319267 (1994-06-01), Kimura
patent: 5699010 (1997-12-01), Hatanaka
patent: 5883539 (1999-03-01), Kimura
patent: 6043700 (2000-03-01), Hoang
patent: 4-102011

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