Method of making a MOSFET device with reduced sensitivity of thr

Details Method of making a MOSFET device with reduced sensitivity of thr Method of making a MOSFET device with reduced sensitivity of thr

1979-03-12

1981-06-30

Rutledge, L. Dewayne

Metal treatment

Compositions

Heat treating

148187, 357 23, 357 91, H01L 2978, H01L 2126

Patent

active

042760950

ABSTRACT:
A MOSFET device structure is disclosed where the channel region has formed therein a buried layer of dopant of the same conductivity type as the source and drain, so that the depletion layers for the PN junctions at the upper and lower boundaries thereof intersect in the middle of the implanted region, effectively forming a buried insulator layer between the source and drain. The presence of this layer increases the distance between the mirrored electrostatic charges in the gate and in the bulk of the substrate beneath the MOSFET, thereby reducing the sensitivity of the threshold voltage of the device to variations in the source to substrate voltage.

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patent: 4143386 (1979-03-01), Kaiser
patent: 4145233 (1979-03-01), Sefick et al.
Fisher et al., Solid State Electronics, 22 (1979) 225.

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