Trench-defined semiconductor structure

Details Trench-defined semiconductor structure Trench-defined semiconductor structure

1983-12-27

1985-10-15

Edlow, Martin H.

357 49, 357 48, 357 35, 357 55, H01L 2704, H01L 2712, H01L 2972, H01L 2906

Patent

active

045477930

ABSTRACT:
An improved device isolated by a trench formed in an N conductivity type semiconductor substrate is provided which has first and second spaced apart P conductivity type regions butted to a sidewall of the trench. An N+ doped region is disposed adjacent to the sidewall of the trench extending from the surface of the semiconductor substrate to an N+ buried region and interposed between the first and second P type conductivity regions. The dopant concentration in the N+ doped region is higher than that of the semiconductor substrate but not higher than the dopant concentration of the N+ buried region. More particularly, a lateral PNP transistor, isolated within a trench formed in an N type conductivity semiconductor substrate having an N+ buried region, has emitter and collector regions butted against a sidewall of the trench, along with the transistor's base region. A highly doped N+ base segment is disposed within the base region of the transistor adjacent to the sidewall of the trench extending from the surface of the substrate to the N+ buried region, and interposed between the emitter and collector regions.

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Schaible et al., IBM Technical Disclosure Bulletin, "Forming Sidewall Dielectric Isolation . . . ", Mar. 1975, pp. 2893-2894.
Antipov, IBM Technical Disclosure Bulletin, "Prevention of Birdsbeak Formation", Apr. 1981, pp. 4917-4919.

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