Method of manufacturing semiconductor integrated circuit devices

Details Method of manufacturing semiconductor integrated circuit devices Method of manufacturing semiconductor integrated circuit devices

1984-09-05

1985-10-15

Saba, William G.

Metal working

Method of mechanical manufacture

Assembling or joining

29576E, 29578, 29580, 148175, 148DIG50, 148DIG51, 148DIG85, 148DIG117, 156643, 156649, 156653, 156657, 1566591, 357 49, 357 50, H01L 2131, H01L 2176

Patent

active

045465380

ABSTRACT:
A method of making semiconductor integrated circuit devices with narrow and deep isolation regions of polycrystalline silicon and wide and thick isolation regions of thermally grown silicon oxide. A multi-layer of a first silicon nitride layer, a polycrystalline silicon layer, a second silicon nitride layer and a silicon oxide layer are formed on a semiconductor body. A photoresist layer is applied on the surface of the silicon oxide layer. An opening is formed in the photoresist layer and the multi-layer. The silicon oxide layer under the photoresist layer is side-etched through the opening. The exposed polycrystalline layer is converted into another silicon oxide layer. Another opening surrounding the silicon oxide layer is formed to expose surfaces of the semiconductor body. Deep grooves are formed in the semiconductor body.

REFERENCES:
patent: 3900350 (1975-08-01), Appels et al.
patent: 3961999 (1976-06-01), Antipov
patent: 4396460 (1983-08-01), Tamaki et al.
patent: 4471525 (1984-09-01), Sasaki
patent: 4473598 (1984-09-01), Ephrath et al.
Kahng et al., "Method for Area Saving . . . Oxidation . . . Sidewalls", J. Electrochem. Soc. (S.S.T. & T) vol. 127, No. 11, Nov. 1980, pp. 2468-2471.
Hayasaki et al., "U-Groove Isolation . . . Bipolar VLSIC'S", International Electron Devices MTG-82, 1982, pp. 62-65.

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