Metal working – Method of mechanical manufacture – Assembling or joining
Patent
1983-12-12
1985-10-15
Ozaki, George T.
Metal working
Method of mechanical manufacture
Assembling or joining
29578, 29591, 148187, 148188, H01L 21225, H01L 2128
Patent
active
045465355
ABSTRACT:
A semiconductor body having at least a surface region of a first conductivity is provided with a insulating layer over the surface region. A substantially horizontal first conductive layer is formed over the insulating layer. The insulating and first conductive layers are masked and etched to form openings in the layers to the semiconductor body where the source, drain and gate region of the device is desired to be formed. The openings have substantially vertical surfaces on the layered structure. A conformal, highly doped of a second conductivity conductive layer is formed over the openings having these vertical surfaces and over the insulating and conductive layers. The conformal layer is anisotropically etched to substantially remove the horizontal portions of the conformal layer while leaving the openings with a substantially vertical conformal conductive layer on the sides thereof. The body is heated to cause the dopant of a second conductivity to diffuse into the body from the conformal layer to form the source and drain regions and a first insulating layer upon the surface of the first conductive layer and the conformal layer. A second insulating layer is formed over the vertical conformal layer. Then a gate dielectric is formed upon the surface of the semiconductor body between the source and drain regions. Electrical contacts are made to the first conductive layer through the first insulator layer which effectively makes electrical contact to the source and drain regions through the horizontal conductive layer and the vertical conformal conductive layer.
REFERENCES:
patent: 3460007 (1969-08-01), Scott, Jr.
patent: 3484313 (1969-12-01), Tauchi et al.
patent: 3600651 (1971-08-01), Duncan
patent: 3664896 (1972-05-01), Duncan
patent: 3978515 (1976-08-01), Evans et al.
patent: 4209349 (1980-06-01), Ho et al.
patent: 4209350 (1980-06-01), Ho et al.
patent: 4234362 (1980-11-01), Riseman
patent: 4236294 (1980-12-01), Anantha et al.
patent: 4256514 (1981-03-01), Pogge
patent: 4309812 (1982-01-01), Horng et al.
patent: 4359816 (1982-11-01), Abbas et al.
patent: 4366613 (1983-01-01), Ogura et al.
patent: 4378627 (1983-04-01), Jambotkar
patent: 4379001 (1983-04-01), Sakai et al.
patent: 4400865 (1983-08-01), Goth et al.
patent: 4419809 (1983-12-01), Riseman
patent: 4419810 (1983-12-01), Riseman
patent: 4424621 (1984-01-01), Abbas et al.
patent: 4430791 (1984-02-01), Dockerty
patent: 4445267 (1984-05-01), De La Moneda et al.
patent: 4464824 (1984-08-01), Dickman et al.
patent: 4470189 (1984-09-01), Roberts et al.
Abbas et al., IBM TDB, "Self-Aligned Metal Process for Integrated Circuit Metallization," vol. 26, No. 6, Nov. 1983, pp. 2732-2738.
S. A. Abbas et al., IBM TDB, "Extending the Minimal Dimensions of Photolithographic Integrated-Circuit Fabrication Processing", Sep. 1977, vol. 20, No. 4, pp. 1376-1378.
S. G. Barbee et al., IBM TDB, "Virtual Image Structure for Defining Sub-Micron Dimensions", Aug. 1982, vol. 25, No. 3B, pp. 1448-1449.
H. B. Pogge, et al., IBM TDB, "Narrow Line-Width Masking Method", Nov. 1976, vol. 19, No. 6, pp. 2057-2058.
"A New Edge-defined Approach for Sub-micrometer MOSFET Fabrication" by W. R. Hunter et al., IEEE Electron Device Letters, vol. ED-2, No. 1, 1/1981, pp. 4-6.
"Sub-micrometer Polysilicon Gate CMOS/SOS Technology", A. C. Ipri et al., IEEE Transactions on Electron Devices, vol. ED-27, No. 7, 7/1980, pp. 1275-1279.
"A Novel Sub-micron Fabrication Technique", T. N. Jackson et al., IEDM 1979 Conference, pp. 58-61.
"A New Short Channel MOS FET with Lightly Doped Drain" by Saito et al., in Denshi Tsushin Rengo Taikai (Japanese), Apr. 1978, pp. 2-20.
International Business Machines - Corporation
Ozaki George T.
Saile George O.
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