Method for optimally placing components of a VLSI circuit

Details Method for optimally placing components of a VLSI circuit Method for optimally placing components of a VLSI circuit

1991-08-20

1994-09-20

Trans, Vincent N.

Boots, shoes, and leggings

364490, 364489, 364488, G06F 1560

Patent

active

053495365

ABSTRACT:
In a method for placement of components for a VLSI circuit, an initial number of current placements are selected. A greedy optimization is partially performed on each of the current placements. Then, a subset of the current placements which have been partially optimized is selected to be the new current placements. This selection is based on a global cost metric for the current placements. The global cost metric is, for example, based on the total length of all connection line networks for the circuit. The partial optimization and selection are repeated until there is only one current placement. Then, an optimization is performed on the remaining placement to obtain an optimized placement. The optimization is, for example, a completion of the partially performed greedy optimization.

REFERENCES:
patent: 5202840 (1993-04-01), Wong
patent: 5222031 (1993-06-01), Kaida
patent: 5229953 (1993-07-01), Isozaki et al.
patent: 5237514 (1993-08-01), Curtin
"Partioning and Placement Technique for CMOS Gate Arrays" by Odaware et al., IEEE Trans. on Computer Aided Design, vol. CAD-6, No. 3, May 1987, pp. 355-363.
C. M. Fiduccia and R. M. Mattheyses, A Linear-Time Heuristic for Improving Network Partitions Proceedings of the 19th Design Automation Conference, 1982, pp. 241-247.
J. B. Lasserre, P. P. Varaiya, J. Walrand, Simulated Annealing, Random Search, MultiStart or SAD?, Systems and Control Letters 8 (1987) 297-301.
S. Kirkpatrick, C. D. Gelatt, M. P. Vecchi, Optimization by Simulated Annealing, Science, vol. 220, No. 4598, pp. 671-680, May 13, 1983.

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