Logic translator interfacing between five-volt TTL/CMOS and thre

Details Logic translator interfacing between five-volt TTL/CMOS and thre Logic translator interfacing between five-volt TTL/CMOS and thre

1992-12-17

1994-09-20

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307455, 307443, H03K 19018

Patent

active

053492536

ABSTRACT:
A logic translating buffer for low voltage operation for receiving a TTL compatible signal and providing a current mode logic signal. The logic translating buffer includes an emitter coupled differential pair of NPN transistors with the common emitters each being connected to a current source. One of the transistors of the differential pair has a constant voltage bias applied to the base thereof that is equal to the sum of a forward biased PN junction, a forward biased Schottky diode, and the voltage drop across a first resistor. The other transistor of the differential pair is provided a signal that is representative of the logic level input to the translating buffer. A clamping transistor is provided for keeping the other transistor of the differential pair from saturating.

REFERENCES:
patent: 4350906 (1982-09-01), Gillberg
patent: 4910425 (1990-03-01), Ohba et al.
patent: 5013941 (1991-05-01), Jansson
patent: 5025180 (1991-06-01), Kim et al.
patent: 5134309 (1992-07-01), Matsumoto et al.

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