Continuous embedded parity checking for error detection in memor

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371 492, G06F 1110

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054348714

ABSTRACT:
A method of and apparatus for continuous parity checking within a CMOS SRAM memory system. Each cell has added circuitry which permits continuous reading of the binary state of the cell. The states of each cell are combined to produce a parity determination for a given data array. By continuously monitoring parity in this manner, the time of failure as well as the fact of failure can be determined.

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