Method for setting the threshold voltage of a vertical power MOS

Details Method for setting the threshold voltage of a vertical power MOS Method for setting the threshold voltage of a vertical power MOS

1988-02-01

1989-08-22

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 38, 437203, 437228, 148DIG126, 148DIG168, 148DIG51, H01L 2122

Patent

active

048596213

ABSTRACT:
A wafer with a <100> orientation comprises a strongly doped N layer (substrate), a lightly doped N layer (middle layer) and a lightly doped P layer (top layer). A strongly doped N layer (source layer) is diffused into most of the top layer. An oxide layer is grown. A V groove with a flat bottom is anisotropically etched through openings in the oxide layer. The V groove is etched through the source layer and most of the P layer. The bottom of the groove initially is at a level above the junction between the top layer and the middle layer. Exposure to beam of phosphorous ions forms a shallow implanted channel region proximate the walls of the groove. An unwanted implanted region along the bottom of the groove is also formed. A second anisotropic etch, through the same oxide mask, deepens the groove bottom to a point below the junction, removing the unwanted portion of the implanted region along the groove bottom. The implanted concentration of the channel is later reduced as the gate oxide is formed. This method of groove formation can be used to set the threshold voltage of enhancement mode power MOSFETS, without comprising the breakdown voltage. It can also be used to produce depletion mode power MOSFETS with zero-gate on resistance values of a few MILLI-OHM CM.sup.2.

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patent: 4272302 (1981-06-01), Jhabuala
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patent: 4374455 (1983-02-01), Goodman
patent: 4503449 (1985-03-01), David et al.
patent: 4612465 (1986-09-01), Schutten et al.
patent: 4697201 (1987-09-01), Mihara

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