Phase-locked delay loop for clock correction

Details Phase-locked delay loop for clock correction Phase-locked delay loop for clock correction

1996-04-12

1997-07-08

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327161, 327244, 327250, 327 5, 327 12, 327276, 327269, H03L 700, H03K 500

Patent

active

056465645

ABSTRACT:
A controlled delay path inserts a selected delay into a clock distribution circuit to create a total clock delay that is equal to an integer number of clock cycles relative to a reference input clock signal or which produces a selected phase relationship to the reference clock signal. The delay path correction of the invention is particularly useful in circuits having a wide range of possible system clock frequencies or having programmable routing of clock signals, and therefore a wide range of operating delays. A reference input clock signal is directed to a range of selectable voltage controlled delay elements by a phase detector that receives the reference input clock signal and a feedback signal, and that produces an error voltage which adjusts the voltage controlled delay elements to produce an output clock signal. Additional selectable delays may be included that create offset options and allow selection of a leading, lagging, or in-phase reference input clock/output clock relationship. In one form of the invention, an inventer adapted to invert one of the reference input clock and output clock signals, and a divide by N circuit for lowering the clock frequency while roughly adjusting the delay.

REFERENCES:
patent: 4051440 (1977-09-01), Nelson et al.
patent: 4222013 (1980-09-01), Bowers et al.
patent: 4322643 (1982-03-01), Preslar
patent: 5039893 (1991-08-01), Tomisawa
patent: 5052031 (1991-09-01), Molloy
patent: 5068628 (1991-11-01), Ghoshal
patent: 5087829 (1992-02-01), Ishibashi et al.
patent: 5099477 (1992-03-01), Taniguchi et al.
patent: 5109394 (1992-04-01), Hjerpe et al.
patent: 5120990 (1992-06-01), Koker
patent: 5144254 (1992-09-01), Wilke
patent: 5173617 (1992-12-01), Alsup et al.
patent: 5191295 (1993-03-01), Necoechea
patent: 5204564 (1993-04-01), Ochiai
patent: 5208546 (1993-05-01), Nagaraj et al.
patent: 5210509 (1993-05-01), Greef et al.
patent: 5216302 (1993-06-01), Tanizawa
patent: 5220294 (1993-06-01), Ichikawa
patent: 5223755 (1993-06-01), Richley
patent: 5260608 (1993-11-01), Marbot
patent: 5307028 (1994-04-01), Chen
patent: 5355037 (1994-10-01), Anderssen et al.
patent: 5389843 (1995-02-01), McKinney
patent: 5428309 (1995-06-01), Yamauchi et al.
patent: 5430394 (1995-07-01), McMinn et al.
patent: 5463337 (1995-10-01), Leonowich
A. Efendovich, Y. Afek, C. Sella, Z. Bikowsky, "Multi-Frequency Zero-Jitter Delay-Locked Loop", pp. 27.1.1-27.1.4, IEEE 1993, Custom Integrated Circuits Conference.
T. Lee, K. Donnelly, J. Ho, J. Zerbe, M. Johnson, T. Ishikawa, "A 2.5V Delay-Locked Loop for an 18 Mb 500 MB/s DRAM", IEEE International Solid-State Circuits Conference, ISSCC94/Session 18/High-Performance Logic and Circuit Techniques/Paper FA 18.6, 1994.
A. Waizman, "A Delay Line Loop for Frequency Synthesis of De-Skewed Clock", IEEE International Solid-State Circuits Conference, ISSCC94/Session 18/High-Performance Logic and Circuit Techniques/Paper FA 18.5, 1994.

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