Boots – shoes – and leggings
Patent
1981-03-05
1983-02-01
Chan, Eddie P.
Boots, shoes, and leggings
G06F 304, G06F 930, G06F 1300, G06F 900
Patent
active
043719317
ABSTRACT:
A microprocessor system comprising an arithmetical logic unit, a program memory and an external memory, memory address means (including a program counter and a memory reference register) for addressing either the program memory or the external memory. The microprocessor is sequenced by a linear sequencing circuit which can use different size plug-compatible PROMs. An instruction register receives instructions from either program memory or external memory along an instruction bus, which instructions are conveyed via a memory operand register to the arithmetic logic unit. The program memory is provided with a specialized instruction word format. The instruction word format provides: a single bit field for selecting either the program counter or the memory reference register as the source of memory addresses; it provides a function field which defines the route of data transfers to be made; and provides a "source and destination" field for addressing selected source and destination locations.
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Catiller Robert D.
Forbes Brian K.
Burroughs Corporation
Cass Nathan
Chan Eddie P.
Kozak Alfred W.
Peterson Kevin R.
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