Multiport cache memory having read-only parts and read-write par

Details Multiport cache memory having read-only parts and read-write par Multiport cache memory having read-only parts and read-write par

1994-08-24

1997-04-08

Elmore, Reba I.

395431, 395403, 395476, G01F 1208

Patent

active

056196741

ABSTRACT:
A multiport cache memory for exchanging data or instructions with a plurality of arithmetic circuitries independently according to a load instruction or a store instruction provided from a CPU. The cache memory comprises a plurality of read only ports for respectively transmitting data or instructions to each arithmetic circuit according to the load instruction, and a plurality of read/write ports for respectively transmitting the data or the instructions from to each arithmetic circuit according to the load or store instruction.

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