Signaling protocol conversion between a processor and a high-per

Details Signaling protocol conversion between a processor and a high-per Signaling protocol conversion between a processor and a high-per

1996-07-03

1998-12-01

Teska, Kevin J.

395308, 395309, 395280, 395281, G06F 1576

Patent

active

058451072

ABSTRACT:
A method of operation in a computer system having a host processor, a pipelined system bus, and at least one agent, all of which operate in accordance with a first signaling protocol, and a processor that is included in a subsystem that operates according to a second signaling protocol which is incompatible with the first signaling protocol. The method comprises the steps of converting arbiter signals generated by the subsystem processor from the second signaling protocol to the first signaling protocol of the pipelined bus to obtain ownership of the pipelined bus. Next, an outgoing request encoding of the processor is translated from the second signaling protocol to the first signaling protocol. Finally, generating a bus cycle on the pipelined bus from the translated outgoing request encoding in accordance with the first signaling protocol of the pipelined bus.

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