Semiconductor device of an LDD structure having a floating gate

Details Semiconductor device of an LDD structure having a floating gate Semiconductor device of an LDD structure having a floating gate

1985-05-22

1987-05-05

Edlow, Martin H.

357 233, H01L 2978, H01L 2968

Patent

active

046636455

ABSTRACT:
A semiconductor integrated circuit device is provided which includes first field effect transistors of an LDD structure having a floating gate as memory cells and second field effect transistors of the LDD structure as elements other than the memory cells. A shallow, low impurity concentration region of the first field effect transistor which is a part of its source or drain region has a higher impurity concentration than a shallow, low impurity concentration region of the second field effect transistor which is a part of its source or drain region. The device is particularly useful in an EPROM arrangement.

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patent: 4573144 (1986-02-01), Countryman, Jr.
patent: 4590503 (1986-05-01), Harari et al.
"Large Capacity EPROM-Its Various Direction Great Change Since 1M", Nikkei Electronics, 1985, 8.12, pp. 119-137.
Kobayashi, N., Iwata, S., Yamamoto, N., Terada, T., Matsuo, H., "Examination of the Heating Atmosphere in the W-Gate Process", 44th Scientific Lecture Meeting of the Applied Physics Society, Sep. 1983.
Stewart et al., "A 40ns CMOS E.sup.2 PROM," IEEE Int. Solid State Circuits Conf. Digest of Tech. Papers, Feb. 1982, pp. 110 and 111.
Tsang et al., "Fabrication of High-Perf. LDD FET's w/Oxide Sidewall-Spacer Tech.," IEEE Trans. Elec. Dev., vol. ED-29, No. 4, Apr. 1982, pp. 590-596.
Smayling et al., "256-K Dynamic RAM is More Than Just an Upgrade," Electronics, 8/25/83, pp. 135-137.

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