Main signal memory supervisory control system using odd-even alt

Details Main signal memory supervisory control system using odd-even alt Main signal memory supervisory control system using odd-even alt

1997-10-24

1998-12-01

Chung, Phung M.

Excavating

371 491, 371 492, 371 53, G06F 1100

Patent

active

058449248

ABSTRACT:
In a main signal memory supervisory control system which comprises a parity generator, a parity detector, a write address counter and a read address counter, a state management section, a down counter, and a change point detector are arranged as memory supervising means. In this memory supervisory, a state management section receives address generation notifications from the write address counter and the read address counter to calculate and outputs the data accumulation amount of the main signal memory, a down counter subtracts a counter by the read address, sets a predetermined value of a data amount in advance, outputs a change notification when a counter value changes from numerical value "1" to numerical value "0", and loads the predetermined value on the counter, and a change point detector sends an odd-even switching signal of a parity when the change point detector receives the change notification. As a result, an odd-even alternative switching operation for a supervisory parity can be performed even in a memory write system such as an ATM communication system using only effective data, so that supervisory performance for the main signal memory can be improved.

REFERENCES:
patent: 3179921 (1965-04-01), Arthur
patent: 3534403 (1970-10-01), Matarese

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