Vertical double diffused metal oxide semiconductor (VDMOS) devic

Details Vertical double diffused metal oxide semiconductor (VDMOS) devic Vertical double diffused metal oxide semiconductor (VDMOS) devic

1987-04-03

1989-04-18

James, Andrew J.

357 238, 357 20, 357 13, H01L 2978, H01L 2944

Patent

active

048231762

ABSTRACT:
A power field effect device has a high voltage blocking junction which intersects the device surface under the gate electrode. That intersection is a closed plane geometric figure whose center is within the body region of the device rather than in the more heavily doped base region of the device. The figure preferably is everywhere convex and has a maximum width of substantially less than the depletion width, at breakdown, of a corresponding parallel plane junction. The device breakdown voltage is higher than the breakdown voltage of a corresponding junction having a cylindrical edge with a straight axis. In a preferred embodiment, the high voltage blocking junction has a plurality of such intersections with the device surface, each situated beneath a segment of the gate electrode. In a bipolar embodiment, the gate electrode may be omitted.

REFERENCES:
patent: 4561003 (1985-12-01), Tihanyi et al.
patent: 4642674 (1987-02-01), Schoofs

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