Method of recovering a sampling clock in a framed data communica

Details Method of recovering a sampling clock in a framed data communica Method of recovering a sampling clock in a framed data communica

1996-11-06

1998-12-01

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327145, 327165, 375376, H03D 324

Patent

active

058444360

ABSTRACT:
To reduce drift in a sampling clock for framed data, a phase detector senses the time difference between (i) the time when a reference mark for the framed data is received and (ii) the time when the nominal number of oversampling clock cycles between reference timing marks is received. This difference is output to a clock controller which chooses a phase change rate based thereon. This phase change rate is applied to an oversampling clock to continuously, progressively, change the phase of the oversampling clock in a sense which tends to reduce this phase error. The phase changing clock is divided down by a frequency divider to generate a sampling clock. The phase of the oversampling clock is changed by generating multiple, equally spaced, phases of the oversampling clock and progressively changing the selection of the active phase.

REFERENCES:
patent: 5077529 (1991-12-01), Ghoshal et al.
patent: 5574756 (1996-11-01), Jeong

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