Low-profile microelectronic package

Details Low-profile microelectronic package Low-profile microelectronic package

1996-03-26

1998-12-01

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

257737, 257686, 257666, 257778, 257692, 257685, 257774, H01L 2348, H01L 2940, H01L 23495

Patent

active

058443150

ABSTRACT:
A microelectronic package (10) is formed by placing a lead frame (22) onto an adhesive polyimide tape (38). The lead frame (22) includes a plurality of metallic leads (16) and an opening. An integrated circuit die (12) is positioned onto the molding support (38) within the opening such that a non-active face (32) of the integrated circuit die (12) rests against the molding support (38). Wire leads (18) connect an active face (28) of the integrated circuit die (12) to the metallic leads (16). A plurality of metallic bumps (20) are attached to the metallic leads (16), and a polymeric precursor is dispensed. The precursor embeds the active face (28) of the integrated circuit die (12), the inner surface (19) of the metallic leads (16), the wire leads (18), and the metallic bumps (20). The microelectronic package (10) is then heated to cure the polymeric precursor to form a polymeric body (14). The microelectronic package (10) is then capable of being tested and subsequently attached to a printed circuit board (40) to form a low-profile microelectronic assembly (11).

REFERENCES:
patent: 5019673 (1991-05-01), Juskey et al.
patent: 5218759 (1993-06-01), Juskey et al.
patent: 5220489 (1993-06-01), Barreto et al.
patent: 5241133 (1993-08-01), Mullen, III et al.
patent: 5278726 (1994-01-01), Bernardoni et al.
patent: 5285352 (1994-02-01), Pastore et al.
patent: 5334857 (1994-08-01), Mennitt et al.
patent: 5608265 (1997-03-01), Kitano et al.
patent: 5616958 (1997-04-01), Laine et al.
patent: 5677566 (1997-10-01), King et al.

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